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An Outstanding Paper Award Winner at EDI CON USA 2017, this paper investigates SERDES performance in a multi-board system. The goal is to identify the cause of data transmission errors and variability between different differential pairs on the same board and between several boards.  Numerical and experimental investigations are carried out on a test board supporting several interfaces operating at 16 Gbps and above, with recommendations to improve performance.    

Design of PCB interconnects for data channels running at bitrate 50 Gbps and beyond is a very challenging problem that requires analyses and measurements over extremely broad frequency bandwidth from DC to 50 GHz and above. This paper shares our experience in building a practical methodology to make predictable 50 Gbps interconnects models.

This article discusses some of the common SI and EMI issues that can be found using DRCs.

How do you design power for sensitive circuits including LNAs, clocks, and PLL circuits? Although these circuits consume low power, they are sensitive to even very low levels of power rail noise. This EDI CON USA 2017 Outstanind Paper Award wining paper discusses the various noise paths that contribute to the degradation of the sensitive circuit as well as how to optimize, measure, and troubleshoot power supply related noise for these applications.

Each of the five experts presented a different approach to incorporating material properties in simulations to accurately predict a channel’s performance. Read on to see what they had to say.

This paper, presented at EDI CON USA 2017, demonstrates the use of a special probe tip utilized to convert a differential measurement of inductor voltage to a measurement of inductor current. It shows the connection and calibration considerations in the measurement of inductor current, including the digital signal processing algorithms required to compensate for the components in the power supply and the probe tip. It also explains current sharing measurements made in the time and frequency domain using a transient current generator.

It's a fact, the older I get, the dumber I become. I came to that realization while thinking about this eternal question engineers have about placement of high speed DC blocking caps in serial link channels. A few years ago I would have been able to recite the pros and cons without hesitation, but now, after playing manager for a few years, before I answer I have to pause and think about it. Fortunately the answer comes back quickly and I can still sleep at night. I find this topic interesting for a few reasons; one, it's a very practical issue found in almost every high speed design, and second, and perhaps more importantly, it's one of those topics were intuition might lead you the wrong way.

Measuring sub-milliOhms is difficult.  Getting low noise, sub-milliOhm measurements in very small circuits is a bit more difficult.  We recently had the opportunity to support R&D Altanova in performing this difficult measurement, here are some of the results.