It's a fact, the older I get, the dumber I become. I came to that realization while thinking about this eternal question engineers have about placement of high speed DC blocking caps in serial link channels. A few years ago I would have been able to recite the pros and cons without hesitation, but now, after playing manager for a few years, before I answer I have to pause and think about it. Fortunately the answer comes back quickly and I can still sleep at night. I find this topic interesting for a few reasons; one, it's a very practical issue found in almost every high speed design, and second, and perhaps more importantly, it's one of those topics were intuition might lead you the wrong way.

Let’s say you have two options, either to put the DC-Blocking caps next to the driver or to the receiver, you don't know the answer and decide to ask two of your favorite co-workers, one sitting in the office to your right, and the other to your left. You walk right, and ask the first person, since this engineer is more accustomed to think in the time domain, he suggests to place the caps close to the receiver and explains:

*“As the signal propagates through the transmission line from the driver, it gets attenuated and the rise time is degraded, when the signal finally arrives to the capacitor close to the receiver, most of the high frequency energy is gone and there are less reflections, hence transmitting more signal to the receiver“*

Then you walk a couple of offices to your left, and ask your second most favorite SI person, this one with more familiarity in the frequency domain might tell you:

**“ For all passive interconnects, every element in the chain is reciprocal, after concatenation of all the elements, the full topology will be also reciprocal in which case forward and backward transmission are the same, hence the location of the cap really does not matter”**

Hmmm, you get very different answers from both of your trusted co-workers and decide not to speak to them again!!

To help solve this dilemma, my goal is to show you a simple way to methodically analyze the problem by looking at the data in the time and frequency domain. In order to start, we’ll set up a simple topology including a short and long piece of transmission line, a couple of vias and a capacitor close to one of the ends as shown in Figure 1.

Usually a great deal of work is required to create each topology model. In this analysis we’ll bypass all that complexity and use simple behavioral and lumped models to illustrate the concepts. The same theory will apply when the models are more detailed and accurate.

Figure 2 shows the RLGC of the uniform, homogeneous, passive and causal transmission line, with 50 Ohms characteristic impedance, loss tangent of 1.6%, line width of 3mils, and DK of 3.9 with a propagation delay of approximately 173ps/inch at 1GHz.

The vias will be simply modeled with a lumped shunt capacitance of 2pf as shown in Figure 3

Finally the capacitor will be modeled with a series R-L representing the internal part parasitic + two shunt capacitors at each end representing the pads and vias to connect to the traces as shown in Figure 4

Call me crazy, but for the capacitor model, I’ll remove the main series capacitance. This will help establish a DC path for the simulations and further TDR signaling analysis. Even though this might sound weird please consider that most high-speed signaling protocols are dc-balanced and encoded such the lowest frequency content is in the 100~~th~~s of MHz. At those frequencies and above, the model with the series capacitor in place or shorted looks identical as shown in Figure 4 and we are still modeling the parasitic inductance and shunt capacitances present and noticeable at the frequency of interest. After all the models are created and chained together as shown in Figure 1, to answer the original question, we consider two cases:

- Driver at Port-1 and receiver at Port-2 (cap really close to receiver)
- Driver at Port-2 and receiver at Port-1 (cap really close to driver)

We inject a pulse at port-1 and see the response at port-2, and then in the reverse direction (inject at port-2 and observe at port-1). In theory with sufficiently big discontinuities, if our friend on the right was correct, we should see a difference in the pulse at the receiver.

Houston we have a problem, Figure 5 shows no difference whatsoever between the two cases, meaning that for this particular topology and parameters, the location of the capacitor will behave exactly the same whether you place it close to the driver or receiver. Then you vaguely remember what your friend on the left office told you about S-parameters reciprocity (for two port networks passive elements, it means S21 ~~=~~= S12) and now that you see it, you believe it, at this point you are definitely concluding your time-domain friend was wrong and your frequency domain friend was right. But wait…..before you call it done, let’s look a bit deeper.

Now in Figure 6 we plot the TDR and return loss from both ends. On the TDR we can clearly see all the elements of the topology and definitely we see that the TDR from Port-2, closer to the DC-Blocking cap, shows a much bigger discontinuity than the TDR from Port-1, equivalently, in the frequency domain, it can be seen the return loss at Port-2 is much worse than the one at Port-1.

In this case since our topology is not symmetrical we can see that S11 is not equal to S22, perhaps this is what triggered the intuition that the location of the capacitor matters, but the fact remains that in our very simple example the transfer forward and backwards is exactly the same as shown on Figure-5

Before concluding the analysis you decide to do a few more tests. One of the arguments was that the location of the capacitor does not matter. In order to prove that, let's create a topology where the overall length is kept constant at 11" but we will be moving the capacitor from one side towards the center at different increments. In theory we should not see any difference.

And here is where it gets interesting, as can be seen on Figure 7, while moving the capacitor from the driver towards the middle of the transmission line we see several things:

- The signal as seen by the receiver changes and this proves that it is not the same to place caps anywhere in the line.
- But when we decide on a cap position, we can rest assured that driving from the left or from the right will yield the same signal at the receiver.
- As we push the capacitor from the center of the transmission line closer to the driver or receiver, we observe the reflections between the end points riding on the pulse at different times
- When the DC blocking cap is placed really close to either end, we can see the most BW transferred as depicted by the faster rise time on Figure-7

Actually just by simply looking at the resonance locations and eye balling the starting of each resonance, we should be able to retrieve the approximate location of the blocking capacitors from one of the ends.

In Figure 8, after calculating the resonances we get approximately 1.3243", (for the 1" separation), 3.06" for the 3" separation, and 5.07" and 6" for the 5" separation. You might wonder why two blips on the 5" separation. Please note that when the capacitor is placed at 5" from one end, it's at 6" from the other end, since the total length of 11" has been kept unchanged. In the 5" separation case we are seeing the ½ wave resonance on both sides of the capacitor.

Of course all these discontinuities pulses (blips) will continue to go back and forth for several bit times until the natural losses of the transmission line attenuate them. It's then clear that when computing eyes, those blips will interfere with following bits ultimately degrading dramatically the eye seen at the receiver.

You might also be wandering, what would happen to those pesky resonances if there was more losses in the transmission line. Let's give it a try.

In Figure 9, by changing the loss-tangent we can see how the signal in general is degrading, but also the resonances (blips) are smaller, in many cases loss is your friend to attenuate resonances.

Let's do one more experiment. The tests before, were done considering a source driver and input receiver impedance of 50 Ohms, perfectly matched to the transmission line. What would happen if we put the caps close to the driver and change the driver source impedance from 40Ohms to 55Ohms while keeping the receiver constant at 50 Ohms.

We can see in Figure 10, that as expected the steady state value of the voltage when changing the source impedance changes, but the overall amount of discontinuity~~-~~ magnitude is not affected much in this case, but wait, I am not suggesting that the magnitude of the discontinuities at the source and cap won't change the magnitude of the blips, eventually they will. The ½ wave resonance magnitude that I so casually mentioned above will be directly impacted by the difference in value between the transmission line (medium) and the end point discontinuities, actually depending of the discontinuities values, the ½ resonance could transform into a ¼ wave resonance, but this would be a topic for another day.

The point I am making, is that **in our particular case** for a range of source impedances between 40 Ohms and 55 Ohms, the overall shape of the waveform does not seem to be impacted much other than the expected change in the steady state high value of the pulse

If we plot now all the different impedances for two different locations of cap placements as shown in Figure 11, we can see that clearly the dominant factor for the blips is the location and not the source impedance of the driver.

Ok, I lied to you before when I told you the above experiment was going to be the last one, I really, really, really want to do one more. If we remove the cap, the topology used in all these simulations is symmetrical, meaning I have the same amount of discontinuities at both ends. The question is: What would happen if the topology was not symmetrical?

Perhaps there is a connector close to one of the ends, or something like that. In order to try it, I'll simple double the value of one of the end vias (via4 in Figure 1). Then I'll run two cases, the first one with the blocking capacitor, 10" from via4, and the second one, with the blocking cap only 1" from via4 (the big via)

From Figure 12, both from the time and frequency domain, it is clear these two topologies are not the same. In this case we can see a bigger reflection when the DC-Blocking cap is closer to the 4pf via (via4). Don't conclude that placing the cap closer to the higher discontinuity side is the worse choice, it might not be, it's difficult, if not impossible to say for every case, it really will depend on your topology and the kind of discontinuity and how can you use those discontinuities to place the cap in a "transparent" way. The key thing is to try to place the capacitor in a way to minimize reflections, whether is the receiver or transmitter it does not matter from a signaling view point.

It's important to notice that there are many other considerations, such as removable interfaces, hot plug capabilities, short current protection, … etc, that will affect the decision of capacitor placement. But from a fundamental SI view point we can conclude that:

- The caps should be placed to minimize as much as possible the discontinuity on the line. As you can imagine, the smaller the capacitor discontinuity, the more transparent it is and the least reflections will be generated by it. In the extreme, if we are able to make the capacitor completely transparent, then it does not matter where it goes.
- Capacitors "in general" should be placed as close as possible to either driver or receiver, hopefully much closer than ½ of a bit time of the signaling rate. This reduces the size of the blips and minimize the degradation of the eye
- When a capacitor location has been established, regardless of how perfect or ugly the topology looks like, it does not matter from which end the topology will be driven (location of driver and receiver)

Now as to the original question, and the advice provided by your friends. Since sometimes I am an optimistic I would say, you realize both were kind of right, it **does** matter where caps go (time domain person), but it **does not **when we settle on an specific topology, either driving from one side or the other (frequency domain person), so you forgive them and go back to talking terms with them.