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Component simulations cannot be properly compared to measurements without de-embedding the test fixture—here’s step-by-step instructions to get the job done well.

Reducing electromagnetic interference (EMI) is a key challenge when designing electronic devices. In this article, we will take a look into EMI challenges, the role of board-level shields (BLS) in reducing EMI, and the key criteria to keep in mind when selecting BLS.

Get a basic EM understanding of resonant behavior, a method for quickly determining resonant frequencies, and a secondary set of metrics to evaluate if a frequency is excited or not.

The RFSoC concept does just that integrating the multi giga sample ADCs and DACs within the same silicon as the SoC, which contains the processing system and programmable logic. This offers a much tighter integrated solution providing the potential for both reduced footprint and power dissipation, while providing a direct sampling RF solution for 5G applications. Integration of ADC and DAC is not on its own sufficient to address the challenges.

Emerging 100 Gigabit Ethernet and 400 Gigabit Ethernet requirements for communication networks have put increasing demands on Internet infrastructure. New methods of design, validation, and troubleshooting to optimize high speed digital channels are being employed in the R&D laboratory. This article discusses new concepts for serial link design and analysis as applied to physical layer test and measurement techniques. Novel test fixtures and signal integrity software tools will be discussed in real world applications in the form of design case studies.

This method enables designers to create 25+ GT/s vias quickly, deliberately, and with much less uncertainty than the traditional technique. Read on to find out more.

Low power, high performance circuits are often plagued by power supply related issues.  This common occurrence is frequently due to mythical (or misapplied) rules-of-thumb.  These rules of thumb often lead us in the wrong direction, making things worse rather than better.  In this article, I’ll highlight some of the most common mistakes engineers make and share some fundamental rules for designing clean power for sensitive circuits.  Applying these rules will result in higher performance, lower cost designs with fewer design iterations.