Figure 1 – Various PCI Express data rates running through 8” of FR4 stripline

With less margin to work with, it becomes increasingly important to move the signal integrity (SI) analysis process further upstream, to address issues and challenges earlier in the design process, allowing mitigation of risk at the back end of the process. This requires some shifts from traditional methodologies, as well as new techniques for modeling the serializer/deserializer, or “SerDes” devices that transmit and receive our high-speed signals. The fruit of this up-front labor is an optimized bill of materials (BOM) for the design, as well as constraints to enable a constraint-driven printed circuit board (PCB) physical layout process. Combined with efficient post-layout interconnect extraction and automated compliance checking, the goal is to be able to confidently sign off your design to fabrication, without major surprises or schedule impacts, and achieve success with your hardware, all while avoiding costly and time-consuming re-spins.

With an initial prototype of your serial link topology in place, and at least placeholder models assigned to the various blocks, you should have a testbench that simulates and passes traffic at the targeted data rate. Now the work begins to replace models with more detailed, more realistic ones as you go through the design process. These models generally fall into one of these general categories:

• IBIS-AMI models for SerDes transmitters and receivers
• Spice models for discretes (ex. AC coupling caps)
• Packages
• PCB traces
• PCB vias
• Connectors

The first step is to do a gap analysis between the models you need for the various blocks in the topology, and the models you have on hand in your library. Augment your testbench with the models that you have, and verify that they simulate cleanly. Next, make list of the models that are missing, contact the model supplier (can be internal or external), and put in requests for the models that you need. Keep track of who you had contact with, the dates of contact, and the status of the model. As you get them, augment your testbench accordingly.

For the purposes of this paper, let’s assume that we are working on a PCI Express Gen 4 serial link, running at 16Gbps. Let’s also assume that we were able to obtain models for the AC coupling caps, packages, and connectors from your suppliers, as well as an IBIS-AMI model for your SerDes receiver. That leaves PCB traces and vias for the board to be eventually designed, and an IBIS-AMI model for your transmitter, which we will assume is currently unavailable from the supplier. Let’s first tackle the PCB structures.

Figure 3 – Taking Manhattan lengths from floorplan for pre-layout trace modeling

Repeat this process for any other trace models needed for your testbench, including microstrip fanout traces, traces connected to either side of AC coupling caps, and so forth.

Figure 5 – Preliminary IBIS model

Enabling Constraint-Driven Design

With the pre-layout testbench built, populated with relevant models, and producing realistic simulation results, it is time to get constraints in place to drive and control the physical layout of the serial link. This may cause some refinement and iteration of the testbench in order to add additional detail, and this is expected. The approach at this point is to parameterize key elements of the testbench, sweep them to quantify their impact on the performance of the overall interface, and constrain those parameters to ensure that our design will meet the specification when finished. In the case of PCI Express Gen 4, the core requirement is for an eye height of at least 15mV and eye width of 0.3UI (which is about 19ps for a 16Gbps data rate), at the target bit error rate (BER) of 1e-12.

So what types of parameters are of interest to sweep? Let’s start with the SerDes devices. They will generally have circuit models with Fast and Slow corner parameters for silicon process/temperature/voltage (PVT), so that aspect should be covered. They may not necessarily be modified or controlled if you are the designer of the PCB, but their effects should be accounted for in sweep simulations, as your PCB will need to work under those conditions. Also, if you are able to obtain package models for the SerDes that cover the min/max range of interconnect parasitics, those should also be included. The same goes for connector and AC coupling cap models.

For the PCB interconnect, start at the transmitter footprint and work your way to that of the receiver. Today’s devices have fine pin pitches, and it is often necessary to neck down the line width and spacing of diff pairs in order to “break out” or “fan out” from the part. Those geometries will generally have a different (higher) impedance than out on the main part of the board, so that will impose an impedance discontinuity. How long can the fanout traces be before they cause a problem? This needs to be considered at the receiver end of the link as well.

Once out on the main portion of the board, the line width and spacing of the diff pair should be swept to replicate the impedance tolerances expected for the PCB (+/-10% is common). Also, it may be impractical to keep the differential traces together all the way across the board. They may need to spread away from each other and be briefly uncoupled to go around an obstacle, or even to connect up to the AC coupling caps. This will change the characteristic impedance. How long can they go uncoupled? How long can the pin escape traces for the cap be? Does that have a significant impact on the result?

And where do you locate the caps? Near the transmitter? The receiver? Does it matter? Sweeping the location can quantify the effect. What about the length tolerance between the positive and negative legs of the differential pair? Do the routed lengths need to be matched to +/- 1 mil in the layout? Or is it OK to allow 10 or 20 mils of difference?

Remember, it is just as important to figure out what does not matter as it is to figure out what does.

Figure 7 – Incorporating constraints into layout to enable constraint-driven design

Efficient Interconnect Extraction

Once physical layout is complete (or at least the serial link differential pairs of interest are routed), post-layout verification can take place. One decision to make is to decide what bandwidth to use for the extraction. To assess this, it is necessary to consider the signals that will be passed through the link. The PCI Express Gen 4 spec refers to rise times of approximately 22ps, measured 10% to 90%. A classic expression relating the rise time to signal bandwidth is:

BW (GHz) = 350 / Trise (ps)

For the case of PCI Express Gen 4, we are looking at signal bandwidth of at least 16 GHz to start with, and likely higher as we factor in equalization. Most engineers would insist on a minimum bandwidth of several times the data rate, which puts us into the 30 to 50 GHz range. So for accuracy, we are clearly in the realm of full wave 3D electromagnetic field solvers, especially for complex, non-planar structures like coupled vias. So the initial inclination is to deploy full wave 3D extraction techniques for these types of serial links.

The problem is computational time. As discussed earlier, the point in the design process where you have detailed interconnect to extract is at the end. And the end of the design cycle is generally the most time-challenged of all, where you can least afford the long computational times. While 3D full wave methods are required for the complex via structures from an accuracy perspective, they are very slow for long, uniform transmission lines, like routed traces in PCBs. Fast, 2D methods still work quite well for those structures, so there is a basic conflict regarding extraction engines.

Figure 8 – Breaking interconnect into multiple regions for cut & stitch

The end results are combined together into one final S-parameter, as if the entire network was extracted with a full wave engine. The advantage of this technique is that it provides full wave accuracy, while providing solution times an order of magnitude (or more) faster than extracting the whole network with only a 3D full wave solver.

At this point, the detailed interconnect model(s) can be plugged back into your simulation testbench for post-layout verification, replacing the PCB trace and via models that were developed in the pre-layout stage.

Simulating with IBIS-AMI Models

By this point in the process, the SerDes component suppliers should have provided any missing IBIS-AMI models, which should be updated in your simulation testbench if they exist and are available. Now the focus shifts to post-layout verification. While it seems that we should be able to simply push the “simulate” button now with all the final models in place, there are often still things to consider with regards to IBIS-AMI models.

As discussed earlier, the algorithmic, or “AMI” section of the IBIS-AMI model represents the equalization functionality of the SerDes. At double-digit data rates, SerDes equalization techniques almost always employ real-time adaptation. To model this, AMI models will often have multiple settings available to the user, so that the equalization can be manually adjusted to best drive their specific channel. To figure out the best combination of settings, it is often left as “an exercise for the reader,” where the SI engineer has to sweep through the multiple combinations and figure out what works best.

With more advanced AMI models, the model itself will incorporate some or all of the adaptation into the channel simulation, closely emulating the behavior of the actual hardware. But even with these types of adaptive models, there are often settings to still review and optimize. For example, consider the following case, which uses a receiver AMI model that incorporates a continuous time linear equalizer (CTLE), automatic gain control (AGC, sometimes referred to as a variable gain amp, or VGA), and decision feedback equalization (DFE).

Figure 9 – Receiver equalization

In this particular model (see Figure 9), each sub-module (CTLE, AGC, and DFE) adapts their settings dynamically, so you may expect that no manual intervention is needed. Running with the default settings, the following is observed (see Figure 10).

While the eye has an opening, the plots of the CTLE, AGC, and DFE coefficients are showing that they do not really converge during the simulation, and continue to bounce around. The initial settings had the AGC module adapting twice as fast as the CTLE module. Speeding up the AGC adaptation to 4x, the CTLE adaptation speed yields these results.

With the quicker AGC adaptation, you can see that the coefficients for all three modules (CTLE, AGC, DFE) settle out and start to converge. But the convergence happens after about 150,000 bits of traffic are passed. So increasing the value of the “Ignore_Bits” parameter in the receiver’s AMI model from 40,000 to 150,000 will remove the first part of the simulation from the results, so the analysis tool evaluates the converged result, as would occur with the real hardware. This produces the result shown in Figure 11.

Figure 11 – Converged receiver equalization settings

Just by adjusting some of the interdependent AMI adaptation model parameters, the eye height in this particular case was improved from 40mV to 85mV at the target BER of 1e-12, an improvement of over 100% (see Figure 12).

This illustrates some of the subtleties associated with simulating with advanced AMI models. The user still needs to carefully review the documentation supplied by the model provider, understand the adjustable settings available to them, and leverage them accordingly.

Another capability related to equalization adaptation is backchannel training (see Figure 13). Many high-speed serial link protocols enable the SerDes receiver to evaluate the signal quality of training patterns sent by the transmitter, decide if it wants more or less equalization from the transmitter, communicate that request back to the transmitter, then receive another training pattern for evaluation. This process is repeated multiple times until the receiver is satisfied with the transmitter settings, then the actual data payload is transmitted with those preferred settings.

Consider the PCI Express Gen 4 example (in Figure 14) with and without the utilization of backchannel training.

Figure 14 – Initial channel simulation results

The initial result (in red) is shown without backchannel enabled. In this case, the transmitter’s AMI model self-optimizes its FFE tap coefficients based on the characteristics of the channel, while the receiver’s AMI model adaptation is done real- time, throughout the channel simulation. The second result (in green) is with backchannel training enabled, and clearly produces a more open eye. The interesting item to note is that if you look at the difference between the FFE tap coefficients used in both cases, you will see that the FFE coefficients have been turned down in the backchannel case. For example, Figure 15 shows how the pre-cursor tap coefficient adapted during the back-channel training:

Here you can see that the pre-cursor tap coefficient starts out initially at an absolute value of almost 0.16, and then over the backchannel training process, gets turned down to the 0.14 range, based on the receiver’s discretion. This enables the receiver’s more advanced equalization functionality to do more of the “heavy lifting” and ultimately produce a better overall result. This shows the importance of enabling the backchannel communication in the channel simulation process, and developing AMI models that closely emulate the real-world behavior of the SerDes devices in actual hardware.

Automated Compliance Checking

With detailed post-layout interconnect in place, and the IBIS-AMI models properly executing, attention can turn to compliance checking for the specific interface of interest, which is PCI Express Gen 4 in our example.

Each interface has some of its own specific criteria to be met. In this case, the PCI Express specification identifies a number of eye-related time domain criteria, frequency domain criteria for the passive interconnect channel, and also the ability to meet a specific jitter tolerance mask.

It can be very time-consuming to evaluate each of these criteria individually, especially if multiple runs are required to sweep corners and multiple channel models. Automated compliance kits for popular serial link standards are often available with simulation tools that can help dramatically speed up your compliance checking and accelerate your time to signoff (see Figure 16).

Figure 16 – PCI Express compliance checks

Automated sweeping of critical parameters and flagging of compliance failures (see Figure 17) enables better coverage of your serial link design, and helps to pinpoint any remaining areas of concern.

Figure 17 – PCI Express compliance results

The other major benefit to using compliance kits is the ability to leverage the associated templates in the pre-layout stage. As discussed earlier, it is critical to get an early testbench built for feasibility trade-offs. But it is common to lack realistic models for some of the necessary blocks at this stage, and sometimes “placeholder” models need to be used. The templates supplied with automated compliance kits will typically come pre-populated with realistic topologies and models, including spec-level models of the SerDes IBIS-AMI models for the transmitter and receiver, built to the reference parameters described in the specification for that particular standard. These templates, and the models associated with them, provide an excellent starting point for your pre-layout testbench development, help minimize the time needed to get up and running, and alleviate the need to start completely from scratch.

Summary

Serial link interfaces with double-digit multi-gigabit data rates have their own unique design challenges. A top-down analysis methodology, starting in the pre-design stage, is a valuable approach to mitigating the associated risks, and avoiding costly and time- consuming re-spins. The fruit of this labor is the wiring rules needed for constraint-driven physical layout. Special care needs to be taken with via structures to control insertion and return losses, and a method with which to enforce known good via structures into layout is essential. IBIS-AMI models are required to represent the adaptive equalization and backchannel functionality seen at these data rates, and can be quickly built to specification if needed. “Cut & stitch” approaches allow full wave accuracy to be deployed where needed for post-layout interconnect extraction, while avoiding the computational penalty of end-to-end full wave 3D extraction. Automated compliance kits can provide acceleration to confident serial link design signoff, while also providing valuable starting points for the pre-layout analysis stage.

Author(s) Biography

Ken Willis is a Product Engineering Architect focusing on SI solutions at Cadence Design Systems. He has nearly 30 years of experience in the modeling, analysis, design, and fabrication of high-speed digital circuits. Prior to Cadence, Ken held engineering, technical marketing, and management positions with the Tyco Printed Circuit Group, Compaq Computers, Sirocco Systems, Sycamore Networks, and Sigrity.

Acknowledgement

The author would like to thank Dr. Kumar Keshavan and Dr. Ambrish Varma of Cadence Design Systems, for the early IBIS backchannel functionality, and other contributions in the serial link analysis space far too numerous to mention.