In 2019 the approval of IBIS (I/O Buffer Information Specification) 7.0 brought much-needed improvements in package modeling capabilities to IBIS. These changes were proposed in the IBIS change request document BIRD189.7. Support was added for a wide variety of package models in Touchstone and IBIS-ISS (IBIS Interconnect SPICE Subcircuit, a subset of Synopsys® HSPICE for interconnects) formats.
Electronic design automation (EDA) tools can import and use these models with minimal effort, making the job of the signal integrity engineer significantly easier when it comes to setting up simulations. IBIS 7.0 also added support for on-die interconnect models between I/O buffers and die pads as well as complex on-die power delivery network models.
One might think that all the package modeling limitations were solved at this point; however, one major restriction was left to the next version of IBIS to solve. This limitation was a one-to-one package pin to I/O buffer connection assumption for signal paths built into IBIS from its early versions. Practically speaking, this meant that you could not model most multi-die packages, such as stacked memories.
The IBIS Interconnect Task Group spent the next two years creating the modeling solution known as Electrical Module Description (EMD); published as the IBIS change request document BIRD202.3. Not only does EMD solve the package model limitation previously described, but it is also a complete replacement for the antiquated IBIS Electrical Board Description (EBD) model format.
EBD was first introduced in IBIS 3.0 and has been used for two decades to model multi-die packages, circuit boards, and modules. EBD significantly restricted connectivity and electrical modeling. With EMD, the DDR4 registered DIMM (RDIMM) shown in Figure 1 can be modeled using widely available Touchstone or IBIS-ISS files.
Printed circuit board traces from the edge connector to the register can be modeled as well as post-register nets routed from the register to the DRAM components. EMD can also be used to model any stacked-die DRAM components on the RDIMM. With EMD, the model maker also has flexibility in partitioning trace models to balance crosstalk and power distribution network (PDN) requirements against model size and complexity that affect final simulation speed.
Several enhancements to the IBIS Algorithmic Modeling Interface (IBIS-AMI) enable the description of equalization features found in the latest high-speed DDRx interfaces. In addition, the IBIS-AMI “back-channel” link training protocol is enhanced to add support for statistical-based optimization of buffer equalization settings.
Another feature supports a simplified on-die PDN model. The new version includes other technical and editorial improvements, offering a significant advance over IBIS version 7.0. With the subsequent release of the official IBIS syntax parser software, IBISCHK7.1.0, model makers can begin upgrading models to support all the features. Even better, EDA tool vendors are already announcing IBIS 7.1 support.