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We’ve come to the end of our first complete year of online publication. Our Editorial Advisory Board (EAB) has done a superb job of nudging us in the right direction, contributing high value technical pieces and reviewing all the technical content submitted to the Signal Integrity Journal. As a final passing favor to the SI, PI and EMC community of readers, we want to leave all of our readers with a year-end holiday gift.

As rated by reader views, here are the Top 10 Articles on Signal Integrity Journal for 2017. Thank you for your readership in 2017, and we look forward to bringing you many more great technical features in 2018!

This paper suggests methodologies for creating a “virtual prototype” of a serial link pre-design and how to create the associated interconnect and SerDes models that go with it. Topics include: using IBIS-AMI models & building your own; the latest interconnect extraction techniques; and using standards-based compliance kits to automate post-layout analysis and signoff for advanced interfaces like PCI Express Gen 4.

An Outstanding Paper Award Winner at EDI CON USA 2017, this paper investigates SERDES performance in a multi-board system. The goal is to identify the cause of data transmission errors and variability between different differential pairs on the same board and between several boards.  Numerical and experimental investigations are carried out on a test board supporting several interfaces operating at 16 Gbps and above, with recommendations to improve performance.    

Design of PCB interconnects for data channels running at bitrate 50 Gbps and beyond is a very challenging problem that requires analyses and measurements over extremely broad frequency bandwidth from DC to 50 GHz and above. This paper shares our experience in building a practical methodology to make predictable 50 Gbps interconnects models.

This article discusses some of the common SI and EMI issues that can be found using DRCs.

How do you design power for sensitive circuits including LNAs, clocks, and PLL circuits? Although these circuits consume low power, they are sensitive to even very low levels of power rail noise. This EDI CON USA 2017 Outstanind Paper Award wining paper discusses the various noise paths that contribute to the degradation of the sensitive circuit as well as how to optimize, measure, and troubleshoot power supply related noise for these applications.