Featured Stories

RSS

I’ve been attending and presenting at DesignCon for 28 years since the first HP High Speed Digital Symposium. And every year, it’s been the same thing, overloaded with too many great talks, too many companies’ latest products to see and too many online friends to finally meet in person. The only thing that has changed is the “too many” part. Needless to say, the many part has only increased.

DesignCon 2018 will feature a 14-track conference covering the latest developments in hardware and high-speed communications design. The conference will also have over 100 technical sessions, three full day boot-camps, and more. Signal Integrity Journal has collected the following exhibition highlights as a preview to what you will see in the exhibition hall.

A Unique Hands-on Opportunity to Characterize Interconnects to 50 GHz, sponsored by the IEEE P370 Standards group and Samtec.

A negative coupling coefficient between decoupling capacitors is expected to result in lower inductance.  While this is generally the case, this can also result in much higher PDN impedance.

We’ve come to the end of our first complete year of online publication. Our Editorial Advisory Board (EAB) has done a superb job of nudging us in the right direction, contributing high value technical pieces and reviewing all the technical content submitted to the Signal Integrity Journal. As a final passing favor to the SI, PI and EMC community of readers, we want to leave all of our readers with a year-end holiday gift.

As rated by reader views, here are the Top 10 Articles on Signal Integrity Journal for 2017. Thank you for your readership in 2017, and we look forward to bringing you many more great technical features in 2018!

This paper suggests methodologies for creating a “virtual prototype” of a serial link pre-design and how to create the associated interconnect and SerDes models that go with it. Topics include: using IBIS-AMI models & building your own; the latest interconnect extraction techniques; and using standards-based compliance kits to automate post-layout analysis and signoff for advanced interfaces like PCI Express Gen 4.

An Outstanding Paper Award Winner at EDI CON USA 2017, this paper investigates SERDES performance in a multi-board system. The goal is to identify the cause of data transmission errors and variability between different differential pairs on the same board and between several boards.  Numerical and experimental investigations are carried out on a test board supporting several interfaces operating at 16 Gbps and above, with recommendations to improve performance.