Featured Stories

Figure 4

Practical DDR Testing: Compliance, Validation and Debug

DDR memory interfaces are becoming increasingly common, and present a unique set of challenges to those designing high-speed embedded systems.  This article will examine what DDR interface testing is all about, concentrating primarily on the physical layer and solutions to common problems.
Read More
EDI CON USA

High Speed Digital Symposium Launches at EDI CON USA 2017

Day two of the three-day conference includes an afternoon symposium on material characterization challenges in high-speed digital design led by session chair Eric Bogatin.

The Electronic Design Innovation Conference and Exhibition (EDI CON) USA announced the addition of a the High-Speed Digital Symposium to its conference line up during the event at the Hynes Convention Center, September 11-13 in Boston, Mass.

Read More
EDI CON

EDI CON USA 2017 Announces Short Courses

Opening day of the conference features in-depth training with three-hour short courses on RF, microwave and high-speed digital design.

The Electronic Design Innovation Conference and Exhibition (EDI CON) USA, the first industry event to bring together RF/microwave and high-speed digital design engineers and system integrators, announced the addition of a full day of training to its conference program at the Hynes Convention Center, September 11-13 in Boston, Mass.


Read More
TE BLS

Reducing EMI with Board-Level Shields

Reducing electromagnetic interference (EMI) is a key challenge when designing electronic devices. In this article, we will take a look into EMI challenges, the role of board-level shields (BLS) in reducing EMI, and the key criteria to keep in mind when selecting BLS.


Read More