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We usually associate problems with the power distribution network (PDN) as from excess VRM noise, or from transient current draw from the core or I/O drivers. But that’s not the only source of PDN noise. Some failures can arise from dull, boring, mundane problems at DC.

This paper focuses on the importance of DCD jitter analysis at higher speed and heavier loading NAND systems, and introduces a statistical approach to DCD jitter analysis.

SIJ talked with Roger Tushingham about how to foster innovation and next-generation circuit materials needs.

Eric Bogatin reviews a presentation by Terence Regan, and shares his thoughts on the topic of high-performance interconnect design and fabrication.

Serial peripheral interface (SPI) is one of the most widely used interfaces between microcontroller and peripheral ICs such as sensors, ADCs, DACs, shift registers, SRAM, and others. This article provides a brief description of the SPI interface followed by an introduction to Analog Devices’ SPI enabled switches and muxes, and how they help reduce the number of digital GPIOs in system board design.

I have lost count of the number of times I have been asked to fix an EMC problem, only to find that a shielding box has been designed or purchased to provide XdB up to fMAX. Or a filter has been designed or purchased with a similar specification, but to reduce cost the filter has been mounted on a printed circuit board (PCB) inside the box, with a cable from it entering or exiting the box through a plain connector.

SIJ talked with Martin Stumpf about industry trends, how to foster innovation, and what today’s designers need most from their test equipment.

The 2018 IEEE EMC+SIPI event returned to Long Beach, CA after last visiting in 2011. The event continues to include Signal Integrity & Power Integrity (SIPI) as part of the conference, reflecting the EMC Society’s influence and focus on this critical topic of engineering design.

Here’s a look at how phase noise converts to time-interval error jitter, which is particularly important to those working on reference clocks for high-speed SERDES or sampling clocks. Read on to see how this can help debug systems to reduce sources of timing noise.