Articles Tagged with ''PCB''

Many designs today include three different value decoupling capacitors, or when using just one capacitor, a small value like 0.1 uF. These recommendations are based on 50-year-old assumptions that do not apply today. It is time to reconsider these out of date, legacy design guidelines.

Return current for a signal always finds a way to flow as close to the signal as possible, thus minimizing the magnetic energy stored in the loop defined by the signal and its return path. So, the return current path is the combination of conduction paths that together minimize the stored magnetic energy. Some elements of the return current path may be part of the design and other elements may be unintentional.

Measured S-parameters and cross-sections of PCB interconnects are used in this paper to identify the parameters of electrical models suitable for statistical analysis of interconnects with manufacturing variations. The constructed models reproduce observed effects of geometry and material properties variations on the loss, delay, and impedance, and they are suitable for yield analysis of interconnects with up to 56 Gbps signals.

What are the greatest technical challenges facing connector designs for future high-speed deployments?Jairo Guerrero of Molex delves into the technical challenges for today’s connectors, the influence of applications such as automotive and data/telecom, and he gives an intriguing glimpse into the product development process at Molex.

The ability to analyze and predict the current/temperature effects of isolated traces is helpful, but the actual temperature of a trace may be different because of uncertainties in the actual trace thickness or board material thermal conductivity coefficient. This article traces the effort to see what PCB board parameters have the most impact in determining trace temperatures, followed by a look at related PCB design considerations. Read on to learn more.

Engineers invest tens to hundreds of thousands of dollars in signal integrity simulation software—the goal being to gain an accurate understanding of how signals are going to behave in the final product. But how do you do that early in the design process without reliable, verifiable electrical properties for the dielectrics incorporated into your design?

When starting a new project, board designers are often overwhelmed when trying to choose appropriate diff pair geometry, board material, and stackup to meet high-speed serial link loss budgets. Part of the printed circuit board (PCB) interconnect challenge is modeling transmission lines accurately. 

Why does a low cost through-hole SMA have a lower bandwidth than a surface mount SMA? The answer will surprise you.

This paper is a case study on causality problems in PDNs during power-aware SI simulations. It covers the causality of a PDN, and it reveals the impact on a design if a causality check is not done on the PDN for the package or board.

If performance matters, if the interconnects are not transparent, or if you want to develop good habits, you will want to incorporate these seven habits in your next two layer board design.