“The biggest technical challenge is the shift into 112 Gbps over copper, for which traditional architecture enablers such as PCB via/trace do not have viable technologies to reduce loss on the channel,” says Jairo Guerrero, General Manager, Enterprise Solutions, Copper Solutions Business Unit, Molex. In a conversation with SIJ, Guerrero provides a detailed glimpse into the product development process as well as insights on the influences of future data rates on connector design. As the General Manager Enterprise Solutions at Molex, he works on high-speed development and has experienced the evolution of  6, 12.5, 25, 56, 112G and future 224G. He holds a Master’s Degree in Industrial Engineering from Tecnológico de Monterrey.

SIJ: In what industries are designers now facing SI/PI concerns that weren’t such a big concern before?

For OEMs focusing on ADAS and autonomous vehicles, there are signal integrity (SI) concerns for high-speed implementations, as this industry historically has not been mainstream in the high-speed arena, and the applications did not require an upscale level of electrical signaling control. However, designers are becoming more familiar with the requirements, and while the applications do not demand such big data rates as other industries, it is still a challenge within this segment. The focus from the industry is to fill the gap and enable the topology of the future, from the silicon all the way to the overall channel construction. We will continue to see the evolution of this segment in the upcoming years, not only inside the vehicle but also on the infrastructure needed to drive seamless communication to the outside links.

Another interesting challenge we are seeing is in the data/telecom space, in which data rates continue to double at a faster pace than before, stretching the physical limits of conventional copper signal transmission. The industry is now reaching future data rates up to 112 Gbps, which is a challenge, especially for longer channels, even with PAM-4 encoding, which drive another set of challenges. Electrical channel enablers, such as silicon, connectors, cable, and PCB companies are working together to find the best solutions to enable these future architectures. A side effect of these solutions does include higher power and the need for creative heat dissipation solutions that have a deep effect on the viability of traditional architectures and the need for new ways to cool these boxes.

SIJ: What are the technical roadblocks for products in these new areas?

We take into consideration all of the variables that would affect the integrity of the channel, either internal, such as power/heat and loss requirements among others, or external, which are mainly driven by ambient temperature, vibration or any other condition the final application would be subjected to.

In addition to those changes, based on the application and mechanical boundaries (such as needed signals), bandwidth requirements, and overall envelope space, we take into consideration all these inputs to define the product development scope and explore the alternative to solve the challenge.

The biggest technical challenge is the shift into 112 Gbps over copper, for which traditional architecture enablers such as PCB via/trace do not have viable technologies to reduce loss on the channel. In the past, the transitions to multiple vias did not have a deep effect on the performance, now it does. However multiple solutions have been designed around that challenge, such as high-speed cables replacing backplanes and even complete end-to-end cable channels.

Another concern is heat, which is driving the need for more dense, smaller interconnects that allow airflow and heat dissipation strategies within the box. It is a balance and compromise between electrical performance and mechanical envelope. This has been a constant in the industry, requiring more dense interconnects that would drive the increased signals coming from the silicon and through the channel.

SIJ: What are the most common SI/PI concerns coming from your datacenter customers? How are advanced backplane technologies changing their design issues? How are you addressing them?

With the deployment of more servers, each one having more compute density, the challenges associated with moving data between processor, networking and storage nodes cost-effectively are exploding; and signal integrity (SI) will be the primary pain point for these densely-packed systems. Solving the SI problem will require a careful balance between signal retimers and low-loss printed circuit board (PCB) materials.

Eventually this segment will migrate their servers into higher speeds and will start adopting some of other strategies to drive their channel needs, not only internally but externally as well.

SIJ: Tell us about one of your latest products of interest to designers concerned with SI/PI issues.

We have many products in our portfolio that drive solutions toward 112 Gbps requirements, from partial or hybrid cable/connector architectures, all the way to end-to-end cable channels. Our goal is to have a flexible menu of options that our customers can choose from, depending on their design requirements, to address their particular electrical and mechanical needs.        

We are very excited about our newest technologies that facilitate high-density connections near the ASIC. For the highest signaling with the lowest loss requirements, we are also implementing separable wire-to-substrate interconnections directly to the top surface of the ASIC substrate. These technologies are close to the signal source/receiver and augment I/O, backplane and cable solutions.     

The products range from the I/O to ASIC, ASIC to backplane, and box-to-box, using a combination of zQSFP or QSFP-DD bypass from the I/O and Impulse/Impulse BiPass in combination with our NearStack connector for the internal cable end. Because we understand the signaling channel relationships, our interconnect designs address the ever increasing data rates and multiple modulation schemes. In order to design interconnects that match system performance and local breakout requirements, Molex works to understand the highest data rate SerDes and chip.

From the system point of view, our designs reduce driver power requirements. Providing 112 Gbps solutions with mechanical flexibility is key to the successful routing of high-speed data while maintaining an architecture that allows for simple thermal solutions.

SIJ: What technical or market challenges had to be overcome to develop these 112 Gbps products?

We are committed to developing innovative products that are focused on future market needs and the solutions needed to enable these architectures. Our R&D and product development teams work to stay 5 to 8 years ahead of the industry. Through our deep customer relationships, we are making sure our technology roadmaps are aligned to adopt a wide range of voice-of-customer inputs. Simply, we manage the transitions between media.

Having exceptional signal integrity means having low reflections, low loss and low crosstalk. This is where our attention to detail in the transitions pays the greatest dividends. In addition to traditional SMT and press-fit terminations, our next-generation engineering methods enable our high volume, state-of-the-art, high-speed precision laser welded twinax-to-terminal manufacturing. 

The implementation for end-to-end solutions have evolved in different stages. First, addressing the longest channel length on the backplane side, by replacing the traditional PCB with high-speed cables in combination with high density backplane interconnects, reducing loss and achieving the margin needed to drive 56 Gbps and prepare for 112 Gbps without major redesign efforts. The key challenge on this initial stage is to maintain the electrical performance consistency from differential pair-to-differential pair and from cable-to-cable, as this consistency and repeatability is key to the final functionality of the channel. To achieve this consistency at volume, we developed a fully automated process that allows us to meet the increased demand we expect from this segment. These were significant challenges and it is the result of years of R&D that set us apart from our competitors.

The next stage is to drive the inside of the box part of the channel via bypass or internal cables as a transition architecture. However, the work done on the previously automated termination and design features made this transition easier from a product development perspective.

SIJ: How do you foster innovation at Molex?        

Innovation is essential to the success of our customers and to Molex.  We believe it is important to look beyond the challenges of today to meet the needs of our customers tomorrow, and this means we must encourage innovation at all levels of the company. We accomplish this in many ways.   Jairo Guerrero

Our R&D investments are higher than the industry average. We collaborate with our customers on new solution design and development. We also know that innovation does not always come from those working on new solution initiatives. Molex has a program called The Innovation Challenge, which we run every two years, where we ask employees to come forward with new ideas to solve industry challenges. It is also exciting to see innovation come alive in so many industries.  Molex has a subsidiary called Molex Ventures which focuses on finding the right investments that will strategically affect our business today and transform it tomorrow. Molex Ventures also connects startup companies with the resources they need for innovation and commercial growth including incubators, angel groups, venture capital firms and other corporate venture capital organizations. 

Because innovation and quality go hand-in-hand, we are continuously working to improve our manufacturing processes. Our commitment to reducing manufacturing costs as we invest has driven us toward a trend of more efficient operations. While our reach remains global, our processes have become more streamlined over the years, ensuring an on-time delivery of quality products to our customers. We are widely known for the quality and reliability of our solutions — and we’re committed to helping customers build products that improve the world.

SIJ: How do you engage customers in training?

Customer training is a critical part of the new product development process. With all new solutions, especially with products that disrupt the status quo, we work very closely with customers to make sure there is a good understanding of the functionality and process requirements to assure a successful launch and minimize time to market.

Our priority is to make sure our customers are having a seamless transition from design to new product introduction and mass production by having our design and process engineering teams on-site working with their team and also at their production site, addressing any questions with on-hand support.

SIJ: How have your customers’ training needs changed over the last 5-10 years? How have you responded to that change?

Over the years our customer training has absolutely adapted. Due to the changes needed to enable the different architectures or electrical or mechanical challenges, we collaborate with our customers to work together on the implementation of the new designs. One example is the transition from traditional midplane architectures to orthogonal direct interconnects. This basically removed the need to have a midplane and a connector on each side, avoiding the electrical discontinuities associated with the transitions from connector to vias and the connector on the other side, and also allowing for air to move more freely in between the boards.

We knew that we needed to work with our customers to help address the stacked tolerances needed for this architecture to work, which at the end became mainstream for current and next-generation applications. As the new implementations become more complex, and become more end-to-end solutions, our approach is to be close to our customers more than ever to hand guide them on their design and get them out to market on time.