When starting a new project, board designers are often overwhelmed when trying to choose appropriate diff pair geometry, board material, and stackup to meet high-speed serial link loss budgets. Part of the printed circuit board (PCB) interconnect challenge is modeling transmission lines accurately.

At high frequencies, conductor and dielectric losses lead to dispersion of the transmitted signal. The total loss of the transmission line is the sum of dielectric and conductor losses.

Neglecting conductor roughness can be problematic, especially when trying to meet the latest industry standards for 28 GB/s non-return to zero (NRZ) or 56 GB/s pulse amplitude modulation-4 level (PAM-4). Furthermore, failure to correct the dielectric constant (Dk) from manufacturers’ data sheets due to conductor roughness can lead to inaccuracy in phase delay and characteristic impedance prediction.

Many electronic design automation (EDA) tools include the latest models for conductor surface roughness and wideband dielectric properties. However, obtaining the right parameters to use is always a challenge for designers.

Some people advocate using the design feedback method. This involves designing, building, and measuring a test coupon. After modeling and tuning various parameters to best fit measured data, material parameters are extracted and used in channel modeling software to design the final product.

The problem with this approach for many small companies is: time, resources, and money.

- Time to define stackup and test structures.
- Time to actually design a test coupon.
- Time to procure raw material: can take weeks, depending on scarcity of core/prepreg material.
- Time to fabricate the bare PCB.
- Time to assemble and measure.
- Time to cross-section and measure parameters.
- Time to model and fit parameters to measurements.

Then there is the issue of resources, which include having the right test equipment and trained personnel to get trusted measurements.

In the end, this process ultimately costs more money, and material properties are only accurate for the sample from which they were extracted for the software and roughness model used. There is no guarantee extracted parameters reflect the true material properties. There will be variation from sample to sample built from the same fab shop and more so from different fab shops because they have a different etch line and oxide alternative process.

But, as Eric Bogatin often likes to say, “Sometimes an O.K. answer now is better than a good answer late.” Many signal integrity engineers, for various reasons, have to come up with an answer sooner rather than later.

So where do we get these parameters? Often the only sources are from manufacturers’ data sheets alone. But in most cases, the numbers do not translate directly into parameters needed for the EDA tools.

In this article I will show:

- How to determine effective dielectric constant (D
_{keff}) due to roughness from data sheets alone. - How to apply my simple Cannonball stack model to determine roughness parameters needed for Huray model from data sheets alone.
- How to apply these parameters in popular EDA software.
- How to pull it all together with a simple case study.

But before we get into it, it is important to give a bit of background on material properties and PCB fabrication process.

### Electro-deposited Copper

Electro-deposited (ED) copper is widely used in the PCB industry due to its low cost. A finished sheet of ED foil has a matte side and drum side. The matte side is usually treated with tiny nodules and is the side bonded to the core laminate. The drum side is always smoother than the matte side. For high frequency boards, sometimes the drum side of the foil is treated instead and bonded to the core. In this case it is known as reversed treated foil (RTF).

IPC-TM-650-2.2.17A defines the procedure for determining the roughness or profile of metallic foils used on PCBs. Profilometers are often used to quantify the roughness tooth profile of ED copper.

Nodule treated tooth profiles are typically reported in terms of 10-point mean roughness (R_{z}). Some manufacturers may also report root mean square (RMS) roughness (R_{q}). For standard foil this is the matte side. For RTF it is the drum side. Most often the untreated, or prepreg side, reports average roughness (R_{a}) in manufacturers’ data sheets.

With the realization of roughness having a detrimental effect on insertion loss (IL), copper suppliers began providing very low profile (VLP) and ultra-low profile (ULP) class of foils. VLP foils have treated roughness profiles less than 4 μm while ULP foils are less than 2 μm. Other names for ULP class are HVLP or eVLP, depending on the foil manufacturer.

It is important to obtain the actual vendor’s copper foil data sheet used by the respective laminate supplier for accurate modeling.

### Oxide/Oxide Alternative Treatment

In order to promote good adhesion of copper to the prepreg material during the PCB lamination process, the copper surface is treated with chemicals to form a thin, nonconductive film of black or brown oxide. The controlled oxidation process increases the surface area, which provides a better bond between the prepreg and the copper surface. It also passivates the copper surface to protect it from contamination.

Although oxide treatment has been used for many years, eventually the industry learned that the lack of chemical resistance resulted in pink ring, which is indicative of poor adhesion between copper and prepreg. This weakness has led to oxide alternative (OA) treatments which rely on some sort of etching process, but no oxide layer is formed.

With the push for smoother copper to reduce conductor loss, newer chemical bond enhancement treatments, working at the molecular level, were developed to maintain copper smoothness, yet still provide good bonding to the prepreg.

Since OA treatment is applied to the drum side of the foil during the PCB fabrcation process, the OA roughness numbers should be used instead of R_{a} specified in foil manufacturer’s data sheets. RTF foil is modeled differently and discussed later in the case study.

### Tale of Two Data Sheets

Everyone involved in the design and manufacture of PCBs knows the most important properties of the dielectric material are the dielectric constant (D_{k}) and dissipation factor (D_{f}).

Using D_{k}/D_{f} numbers for stackup design and channel modeling from “marketing” data sheets, like the example shown in *Figure *** 1**, will give inaccurate results. These datasheets are easily obtained when searching laminate supplier’s websites.

_{}Fig. 1 Example of a "Marketing" data sheet easily obtained from laminate supplier's web site. Source Isola Group.

Instead, real or “engineering” data sheets, as shown in* Figure 2*, which are used by PCB fabricators to design stackups, should be used for PCB interconnect modeling. These data sheets define the actual thickness, resin content, and glass style for different cores and prepregs. They include D

_{k}/D

_{f}over a wide frequency range; usually from 100 MHz to 10 GHz.

_{ }**Fig. 2 Example of a "Engineering" data sheet showing Dk/Df for different glass styles and resin content over frequency. Source Isola Group**

Effective D_{k} Due to Roughness

Many engineers assume Dk published is the intrinsic property of the material. But in actual fact, it is the effective dielectric constant (D_{keff}) generated by a specific test method. When simulations are compared against measurements, there is often a discrepancy in D_{keff4} due to increased phase delay

caused by surface roughness.

D_{keff} is highly dependent on the test apparatus and conditions of how it is measured. One method commonly used by many laminate suppliers is the clamped stripline resonator test method, as described by IPC-TM-650, 2.5.5.5, Rev C, Test Methods Manual.

The measurements are done under stripline conditions usinga carefully designed resonant element pattern card made with the same dielectric material to be tested. The card is sandwiched between two sheets of unclad dielectric material under test. Then the whole structure is clamped between two

large plates; each lined with copper foil and are grounded. They act as reference planes for the stripline.

This method assures consistency of product when used in fabricated boards. It does not guarantee the values directly correspond to design applications.

This is a key point to keep in mind, and here is why.

Since the resonant element pattern card and material under test are not physically bonded together, there are small air gaps between the various layers that affect measured results. The small air gaps result in a lower D_{keff} than what is measured in real applications using foil with different roughness bonded to the same core laminate. This is the primary reason for phase delay discrepancy between simulation and measurements.

If D_{k} and R_{z} roughness parameters from the manufacturers’ data sheets are known, then the effective D_{k} due to roughness (D_{keff}__{rough}) of the fabricated core laminate can be estimated by Simonovich:^{1}

^{}

where H_{smooth} is the thickness of dielectric from data sheet; R_{z }is 10-point mean roughness from data sheet; D_{k} is dielectric constant from data sheet.

Most EDA tools include a wideband causal dielectric model. To use it, you must enter D_{k} and D_{f }at a particular frequency. I found it is usually best to use the values near the Nyquist frequency of the baud rate.

### Modeling Copper Roughness

“All models are wrong but some are useful”—is a famous quote by George E. P. Box who was a British statistician in the mid-20^{th} century. The same can be said when using various roughness models.

For example many roughness models require RMS roughness numbers, but often R_{z} is the only number available in data sheets, and vice versa. If R_{z} is defined as the sum of the average of the five highest peaks and the five lowest valleys of the roughness profile over a sample length, and R_{q} is the RMS value of that profile, then the roughness can be modeled as a triangular profile with a peak to valley height equal to R_{z}, as illustrated in * Figure 3*.

If we define the RMS height of the triangular roughness profile is equal to Δ, then

And likewise, if we assume Δ ≈ R_{q' }then

Several modeling methods were developed over the years to determine a roughness correction factor (K_{SR}). When multiplicatively applied to the smooth conductor attenuation (α_{smooth}), the attenuation due to roughness (α_{rough}) can be determined by

Huray Model

In recent years, the Huray model3 has found its way into popular EDA software due to the continually increasing need for better modeling accuracy. The model is based on a nonuniform distribution of spherical shapes resembling snowballs, and stacked together forming a pyramidal geometry.

By applying electromagnetic wave analysis, the superposition of the sphere losses can be used to determine the total loss of the structure. Since the losses are proportional to the surface area of the roughness profile, an accurate estimation of a roughness correction factor (K_{SRH}) can be analytically

solved by Huray^{3}:

Although it has been proven to be a pretty accurate model, it relied on analysis of scanning electron microscopy (SEM) pictures of the treated surface and tuning of parameters for best fit to measured data. This is not a practical solution if all you have is roughness parameters from manufacturers’ data sheets.

### Cannonball-Huray Model

Building upon the work already done by Huray, and using the Cannonball stack principle, the sphere radius and flat base area parameters are easily estimated solely from roughness parameters published in manufacturers’ data sheets.

As illustrated in * Figure 4*, there are three rows of equal sized spheres stacked on a square tile base. Nine spheres are on the first row, four spheres in the middle row, and one sphere on top. This stacking arrangement is known as close-packing of equal spheres, but more commonly known as the Cannonball stack due to the method used by sailors to stack actual cannonballs aboard ships.

If we could peer into the stack and imagine a pyramid lattice structure connecting to the center of all the spheres, then the total height is equal to the height of two pyramids plus the diameter of one sphere.

Given the height of the Cannonball stack (Δ) is equal to the RMS value of the peak to valley roughness profile; then from method described in Simonovich^{2}, determining the sphere radius (r), from R_{z }found in data sheets, can be further simplified

and approximated as

and base area (A_{flat}) as

Because the model assumes the ratio of A_{matte}/A_{flat} = 1, and there are only 14 spheres, the original Cannonball-Huray model can be further simplified to:

where K_{CH} (f) = Cannonball-Huray roughness correction factor, as a function of frequency; δ (f) = skin-depth, as a function of frequency in meters; r = the radius of spheres in meters (Equation 6).

### Cannonball-Huray Model for Popular EDA Tools

Several popular EDA tools ask for input parameters for the Huray model that are not easily apparent unless you go searching in their help manual.

Ansys^{11} and Cadence^{12} tools require surface ratio (sr) and nodule radius (r) as input parameters. In this context, surface ratio is defined as surface area of spheres divided by the base area.

Because the Cannonball model always has N=14 spheres and base area (A_{flat}) is always 36r^{2}, r^{2} cancels out and sr can be simplified to

Nodule radius (r) is calculated from Equation 6.

Simbeor electromagnetic signal integrity software, from Simberian Inc.,^{10} requires two parameters; roughness factor (RF1) and sphere radius (SR1). Because the Cannonball model always has N=14 spheres and base area (A_{flat}) is always 36r^{2}, r^{2} cancels out and RF1 can be simplified to

Sphere radius (SR1) is calculated from Equation 6.

Mentor Hyperlynx^{13} and Polar Instruments Si9000e^{4} include the Cannonball-Huray model as an option, so all that needs to be entered is R_{z} for drum and matte side of the foil directly.

Megtron-4 RTF Case Study

To test the accuracy of the model, measured data from a test platform, courtesy of Ciena Corporation shown in * Figure 5*, was used for model validation. The 5 in. de-embedded Sparameter data was computed from a 1 in. and 6 in. differential stripline traces.

The PCB was fabricated with Panasonic Megtron-4 (Meg-4) 1067 core and prepreg, with 0.5 oz. RTF. The copper foil used for the build was known in advance, and roughness parameters were obtained from the copper foil vendor’s data sheet. * Table 1* summarizes the PCB design parameters, dielectric material properties and copper roughness parameters obtained from respective manufactures’ data sheets.

An oxide or OA treatment is usually applied to the copper surfaces prior to final PCB lamination. When it is applied to the matte side of RTF, it tends to smoothen the macro-roughness slightly (Marshall).^{14} At the same time, it creates a surface full of microvoids which follows the underlying rough profile

and allows the resin to fill in the cavities, providing a good anchor. Typically 50 μin (1.27 μm) of copper is removed by OA treatment,^{15} thereby reducing the roughness to 2.13 μm.

From Table 1 and by applying Equation 1, D_{keff }of core and prepreg due to roughness were determined to be:

Next, the Cannonball model’s sphere radiuses, for matte and drum side of the foil, were determined to be:

Because most EDA tools only allow a single value for the radius parameter, the average radius (r_{avg}) was determined to be:

Polar Instruments Si9000e4 was the primary tool used for this case study because it is a popular tool used by many board shops for designing stackups. It has a simple user interface which helps getting the answer quickly, with less chance of mistake.

As mentioned earlier, it includes the Cannonball-Huray model, so all that was needed was to enter R_{z} for drum and matte side after etch treatment from Table 1, then the other roughness parameters were automatically computed, simplifying the whole procedure.

The wideband causal dielectric model option was used to model dielectric properties over frequency. Effective D_{k} due to roughness for core and prepreg, calculated above, were substituted instead of data sheet values.

After the transmission lines were modeled and simulated, the S-parameter results were saved in touchstone format.

Keysight ADS^{5} was used for further simulation analysis and comparison.

D_{keff} can be derived from phase delay. This is also known as time delay (TD) and is often used as a metric for simulation correlation accuracy for phase. TD, as a function of frequency, in seconds, is calculated from the unwrapped measured transmission phase angle, and is given by

where c = speed of light (m/s); Length = length of conductor (m).

* Figure 6* compares the simulated results vs measurement of a 5 in., de-embedded stripline trace. The red plots are measured and blue plots are simulated. Differential IL is shown on the left and D

_{keff }is shown on the right. As can be seen, there is excellent correlation for IL but measured D

_{keff }at

10 GHz is higher than simulated.

Although D_{keff} is close to measurements, it is non-causal because Polar software only applies the roughness correction factor to the real part of the internal impedance of the metal. This is evident by the difference in shape between the two curves, especially less than 10 GHz.

Because Simbeor’s Huray-Bracken roughness model^{10} applies the roughness correction factor to both the real and imaginary part of the internal impedance of the metal, it was then used to compare the causal and non-causal conductor model differences. The model requires two parameters:

Roughness Factor (RF1) and Surface Roughness (SR1) as shown in * Figure 7*.

The average sphere radius from Equation 11 and RF1 from Equation 10 was entered to the roughness parameter panel.

After modeling and simulation the results are shown in * Figure 8*. There was no significant change in IL, and when Huray-Bracken causal metal roughness model was applied, simulated D

_{keff}matches measurements almost exactly. This is remarkable, considering there was no additional tuning

or curve fitting parameters from manufacturers’ data sheet values.

* Figure 9* shows simulated vs measured results for time domain transmission (TDT) single bit response (SBR) on the left and time domain reflectometry (TDR) on the right. The SBR shows the causal model is almost an exact fit to measurements. But even though the non-causal SBR shows slight differences in rise and fall time shape and delay, the non-causal model is still useful.

The TDR impedance shows that even though the exact stripline cross-section geometry is unknown, both simulations are within 10 percent of measurements. The causal model has slightly higher characteristic impedance and the rising slope is a better match to measured results. Nevertheless, the noncausal model is still useful.

Conclusion

By using Cannonball-Huray model, with copper foil roughness and dielectric material properties obtained solely from manufacturers’ data sheets, practical PCB interconnect modeling for high-speed design is now achievable using commercial field-solving software employing Huray model.

The non-causal model for conductor loss does not adversely affect simulation results when compared to measurements and should not disqualify EDA tools that have not included a causal metal loss model.

*Article was published in the SIJ July 2019 Print Issue, Technical Feature: Page 26**.*

Acknowledgment

This article is from a condensed version of a DesignCon 2019 Best Paper Award paper titled, “PCB Interconnect Modeling Demystified.”^{16}

References

1. B. Simonovich, “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness,” DesignCon 2017 Proceedings, Santa Clara, Calif., 2017.

2. L. Simonovich, “Practical Method for Modeling Conductor Roughness using Cubic Close-Packing of Equal Spheres,” 2016 IEEE International Symposium on EMC, Ottawa, ON, 2016, pp. 917−920.

3. P. G. Huray, “The Foundations of Signal Integrity,” John Wiley & Sons Inc., Hoboken, N.J., 2009.

4. Polar Instruments Si9000e Version 2017, www.polarinstruments.com/index.html.

5. Keysight Advanced Design System Version 2017, www.keysight.com/en/pc-1297113/advanced-design-system-ads?cc=US&lc=eng.

6. Panasonic Industrial Devices and Solutions Division, https://industrial.panasonic.com/ww.

7. Isola Group S.a.r.l., www.isola-group.com/.

8. Ciena Corp., www.ciena.com.

9. V. Dmitriev-Zdorov, B. Simonovich, and I. Kochikov, “A Causal Conductor Roughness Model and its Effect on Transmission Line Characteristics”, DesignCon 2018 Proceedings, Santa Clara, Calif., 2018.

10. Simberian Inc., www.simberian.com/.

11. ANSYS Inc., www.ansys.com/.

12. Cadence Design Systems Ltd., www.cadence.com/.

13. Mentor Hyperlynx, www.mentor.com/pcb/hyperlynx/.

14. J. A. Marshall, “Measuring Copper Surface Roughness for High Speed Applications,” IPC APEX Expo 2015.

15. Macdermid Enthone, Multibond MP, Inner Layer Oxide Alternative Bonding, https://electronics.macdermidenthone.com/products-and-applications/ printed-circuit-board/surface-treatments/innerlayer-bonding.

16. B. Simonovich, “PCB Interconnect Modeling Demystified,” DesignCon 2019, Proceedings, Santa Clara, Calif, 2019.