Larry Smith

Larry  is a Principal Signal Integrity engineer at Micron specializing in Power Integrity since August 2018, and he is a member of the SIJ Editorial Advisory Board.  Prior to joining Micron, he was a PI engineer at Qualcomm in the mobile computing space beginning in 2011. He worked at Altera from 2005 to 2011 and Sun Microsystems from 1996 to 2005, where he did development work in the field of signal and power integrity. Before this, he worked at IBM in the areas of reliability, characterization, failure analysis, power supply and analog circuit design, packaging, and signal integrity. Mr. Smith received the BSEE degree from Rose-Hulman Institute of Technology and the MS degree in material science from the University of Vermont. He has more than a dozen patents and has authored numerous journal and conference papers.  His most recent work is a book entitled “Principles of Power Integrity for PDN Design” published by Prentice Hall in 2017 with Dr Eric Bogatin

ARTICLES

Target Impedance Is Not Enough

Target impedance has become a standard tool when designing a power distribution network (PDN). It establishes a limit to the highest impedance the power rail on the die should see looking into the PDN. If the PDN impedance stays below this limit, even the worst-case transient current from the die will generate an acceptably low rail voltage noise.


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VRM Modeling: A Strategy to Survive the Collision of Three Worlds

This paper reviews four levels of VRM models that VRM designers, board level interconnect designers, semiconductor designers, and product managers often use to explore design tradeoffs throughout the PDN system. The choice of which one to use involves considering engineers’ levels of expertise and what problems they expect to analyze. Some tradeoffs and relative merits of the models are described.


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