Alex Manukovsky is a Technical lead of the Signal & Power Integrity team at Intel Networking Division, responsible for the development of indoor link simulator for high speed serial links, combining both traditional methods of frequency and time domain simulation along with machine learning capabilities. Alex focuses on simulation to lab correlation for high speed serial links for PCIe and Ethernet technologies. His past work focused on channel modeling, robust de-embedding and calibration techniques for VNA and TDR. His experience includes developing test equipment for compliance testing of serial I/O's as well as lab measurement methodologies for volume testing and Si/Pi simulations. Alex joined Intel in 2010 after receiving his BSc in Electrical Engineering from the Technion – Israel Institute of Technology. In 2019 he received his Master's degree in System Engineering from the Technion – Israel Institute of Technology.
Measured S-parameters and cross-sections of PCB interconnects are used in this paper to identify the parameters of electrical models suitable for statistical analysis of interconnects with manufacturing variations. The constructed models reproduce observed effects of geometry and material properties variations on the loss, delay, and impedance, and they are suitable for yield analysis of interconnects with up to 56 Gbps signals.