Dror Haviv

Dror Haviv received his Master of Science (M.Sc) degree in electrical engineering with honors from the Electromagnetic program at Ben-Gurion University (Beer-Sheva, Israel). With comprehensive multidisciplinary vision in signal and power integrity (PCB, Package, Die), he has years of design, analysis, measurement, and teaching experience in the signal/power integrity (SI/PI) field behind him. In the last 15 years, Dror has been serving as a lecturer for signal and power integrity. 

These days, Dror serves as a senior signal/power integrity technical expert at Mobileye Vision Technologies. From 2020 to 2023, he served as a Technical Lead at the signal and power integrity team at Western Digital ASIC platform engineering organization. His job duties included flash controllers (ASIC), signal and power integrity design and analysis, silicon die and package co-design and analysis, modeling, system level SI/PI simulations, and correlation analysis of die-package SI/PI parameters between simulation and measurement results.

From 2010 to 2019, Dror served as signal integrity focal point and architect with RAFAEL R&D division. As a signal integrity architect, he designed, analyzed, simulated, and measured dozens of systems and PCBs with high-speed interfaces. As a focal point, he has qualified, educated, trained, and supervised many engineers in the signal integrity field. Simultaneously, he served as a senior signal integrity cooperate researcher and has conducted several research projects in the field.


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An Alternative Approach to Analyzing Far-End Crosstalk

Reducing various types of noise such as reflections, mode-conversion, return-path bounce, and crosstalk becomes a serious challenge in signal integrity designs of high data-rate interfaces. In this article, Dror Haviv focuses on the analysis and properties of the FEXT, presenting an alternative way to analyze the FEXT and its properties using the superposition theory of the differential signal and the common signal.

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Breaking Loop Inductance into Pieces

Inductance and resistance are fundamental to the design and analysis of Power Delivery Networks (PDNs). Excessive inductance and resistance can cause several severe power and signal integrity problems, as well as design failure. As we have seen, inductance can certainly be a confusing parameter. The type of the extracted resistance and inductance (loop or partial) depends on how the ports are connected to the model in the simulation. Consequently, their connection in the electrical circuit and the level of voltage details we can get from the simulation results will be determined. In many cases, it is required to know the voltage drop on the PWR path and on the GND path separately, therefore it is necessary to use partial inductances and resistances. The method of expressing SLI with partial inductances and the ideas behind it are briefly described in this paper.

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How to Stop Your Differential Vias from Leaking

Can common via structures transfer any data rate or are they limited with a defined bandwidth? If so, what limits its bandwidth? And what can be done when the bandwidth of the signal is greater than the bandwidth of the G-S-S-G structure? This technical feature from Dror Haviv explains.

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