Technical Articles

A Study of Forward Error Correction Codes for SAS Channels

This paper evaluates the performance of several choices of Reed-Solomon code and shows how a frame-interleaved RS(30,26) code can achieve 1e-15 bit-error rate (BER) in the presence of burst errors. See the authors conclude that, as data rates go higher, current 128b/130b encoding is not a good option as the two-bit 01/10 overhead suffers due to its Nyquist pattern property.


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VRM Modeling: A Strategy to Survive the Collision of Three Worlds

This paper reviews four levels of VRM models that VRM designers, board level interconnect designers, semiconductor designers, and product managers often use to explore design tradeoffs throughout the PDN system. The choice of which one to use involves considering engineers’ levels of expertise and what problems they expect to analyze. Some tradeoffs and relative merits of the models are described.


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Outer Loop Equalization for PCIe Cross-Lane Transceiver Optimization

PCIe Gen4 Standards Margin-Assisted Outer-Layer Equalization for Cross-Lane Optimization in a 16GT/s PCIe Link

PCIe Gen4 enables new wave of innovation to guide inner-loop SerDes optimization assisted by outer-loop system optimization. This paper introduces an outer-layer equalization scheme for managing SerDes inner-layer equalization to optimize overall system-level aggregate performance.


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40 GHz PCB Interconnect Validation: Expectations vs Reality

What does it take to design PCB interconnects with good analysis-to-measurement correlation up to 40 GHz? Is it doable with typical low-cost PCB materials and fabrication process, typical trace width, via back-drilling and the shortage of space to place the stitching vias? This paper reports lessons learned from validation projects with the goal to build a formal procedure for systematic prediction of interconnect behavior up to 40 GHz. Topics include: selection of test structures, connectors and measurement equipment, and analysis uncertainties.

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A Causal Conductor Roughness Model and its Effect on Transmission Line Characteristics

In the GB/s regime, accurate modeling of insertion loss and phase delay is a precursor to successful high-speed serial link designs. We propose a causal (physically meaningful) form of the Hammerstad and Cannonball-Huray metal roughness frequency dependent complex correction factor. Compared to the widely used, non-causal form, it considerably increases the inductive component of internal metal impedance. Transmission lines simulated with a causal version demonstrate increased phase delay and characteristic impedance. By obtaining the dielectric and roughness parameters solely from manufacturers' data sheets, we validate the model through a detailed case study to test its accuracy.


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Introduction to SPI Interface

Serial peripheral interface (SPI) is one of the most widely used interfaces between microcontroller and peripheral ICs such as sensors, ADCs, DACs, shift registers, SRAM, and others. This article provides a brief description of the SPI interface followed by an introduction to Analog Devices’ SPI enabled switches and muxes, and how they help reduce the number of digital GPIOs in system board design.


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Managing EMI and EMC at GHz and Beyond

Tools to Combat Radiated Emissions, for EMC Compliance and Performance Gains

New power-semiconductor technologies like SiC and GaN enable increased efficiency and higher switching frequencies, which allows smaller component sizes. But these gains come at the expense of greater radiated electromagnetic emissions, just as EMC regulations are getting tougher. How can engineers effectively minimize radiated EMI?


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Phase Noise Aliases as TIE Jitter

Here’s a look at how phase noise converts to time-interval error jitter, which is particularly important to those working on reference clocks for high-speed SERDES or sampling clocks. Read on to see how this can help debug systems to reduce sources of timing noise.


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