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This paper covers a study previously presented at DesignCon 2025 in which a novel SI-PI layout optimization methodology and via routing pattern were developed to address challenges and enable UCIe-xA64 connections to achieve 36 Gbps in Organic Interposer packaging. This summary provides an overview of the challenges, innovations, and methodologies presented in the study, offering solutions for high-speed multi-die system integration.

This paper, previously presented at DesignCon 2025, introduces a comprehensive framework for achieving 12.8 Gbps HBM3/4-to-SoC integration using innovative interposer technologies. This summary covers the key methodologies, findings, and implications of the study, focusing on practical solutions to SI-PI challenges in HBM interfaces.

Point2 Technology’s e-Tube offers a compelling alternative to copper cables and optics. It extends copper’s reliability and economics to support terabit-scale data rates in a lightweight, power-efficient, and highly manufacturable form to address short reach, AI cluster scale-up in data centers. With roadmap scalability to multi-terabit and compatibility with standard cable form factors, e-Tube redefines the compute fabric for next-generation AI clusters.

This article presents a simple yet effective method to roll your own TDR using any square wave source, any scope, and an affordable power splitter. This low-cost approach offers a practical and accessible solution for characterizing transmission lines in educational or resource-constrained lab environments. 

In this article, Bert Simonovich explains why material anisotropy is not solely responsible for contributing to Dkeff surrounding a via hole structure. The via barrel conductor roughness and resin content of the as fabricated dielectric pressed thicknesses must be considered and adjusted before applying this heuristic method to calculate Dkxy.

In this article, it is demonstrated that intra-pair skew cannot be properly defined on a screened single pair, as the signal launched in a single wire does not propagate as such along the pair due to inter-wire coupling.

Yuriy Shlepnev of Simberian outlines the fundamental elements of DEA, examines the conditions for its accuracy, and highlights its growing importance in the future of interconnect design.

Many engineers struggle with getting their simulations and measurements to agree. Steve Sandler discusses calibration and de-embedding component measurements to help improve matching with the OMICRON Lab Bode 500.

EM simulators that are optimized for PCB PDN simulations provide an increased level of automation to enable the basics of DC IR Drop, electrothermal, and AC impedance for early detection of design issues. In this article, Heidi Barnes, Steve Sandler, and Benjamin Dannan examine why the ability to optimize a PDN for Z_Target with PCB parasitics in the frequency domain and then export to an end-to-end PI Digital Twin simulation for validation in the time domain should be standard practice for the PI engineer.