Rick Rabinovich

Rick Rabinovich, IEEE802.3 Ethernet voting member, is a Distinguished Engineer at Keysight Technologies, specializing in 3D modeling of electromagnetic structures and PCB stackup optimization for 10G/25G/50G/100G/200G/400 GbE. Former IEEE Communication Society member, Rick was a Senior Principal Design Engineer at Alcatel-Lucent and an Alcatel-Lucent Bell Labs Distinguished Member of the Technical Staff. He has authored several technical articles in the IEEE Communications and EDN magazines and holds two U.S. patents in communications. Rick's previous positions include Hardware Technology Director and Fellow Associate at Spirent Communications, and senior position at Northrop Grumman. Rick holds a BS from the Buenos Aires University Engineering College and attended computer post-graduate courses at Cal State Los Angeles, UCLA, and UCI

ARTICLES

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Path to 400G May Require Alternative Architectures

DesignCon 2025 Best Paper Award Winner

Traditional data-center physical layer architectures have undergone a significant transition due to the growth of east-west traffic within the data center for AI/ML cluster applications. This data growth has driven enormous demand for throughput in both chip-to-chip and chip-to-module channels. In this paper, which was awarded Best Paper Award at DesignCon 2025, the authors explore various physical layer design improvements through simulation and modeling tools.



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Are 1.0 mm Precision RF Connectors Required for 224 Gbps PAM4 Verification?

DesignCon 2024 Best Paper Award Winner

This paper, awarded the Best Paper Award at DesignCon 2024, explores what is meant by bandwidth during the standardization process, the implications of test and verification attached to certain bandwidth requirements, as well as differences between acquisition range, band limited filters, and s-parameters for time domain processing. 


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