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Luis Boluña is a Senior Application Engineer for High Speed Digital Systems and Test Validation for Keysight Technologies. He has extensive experience in both the measurement and simulation of high speed SerDes architectures and backplane designs. His background is Signal Integrity and Mixed Signal Circuit Design. He has worked in Silicon Valley almost 23 years with Cisco Systems, Rambus, Microsoft, and National Semiconductor. His research interests are in system design, testability, simulation, and validation of high speed designs.
Here's a proposed method that improves the accuracy of DDR4 statistical simulation by using the mask correction factor. It presents a validated correlation between measured and simulated data to show that this methodology can be effectively used for DDR4 design
