Luis Boluña

Luis Boluña is a Measurement Scientist for Keysight Technologies. He has extensive experience in both the measurement and simulation of high speed SerDes architectures and backplane designs. His background is Signal Integrity and Mixed Signal Circuit Design. He has worked in Silicon Valley almost 29 years with Agilent, Cisco Systems, Rambus, Microsoft, and National Semiconductor. Luis has two U.S. patents and a Pioneer Award from Cisco Systems. His research interests are in system design, testability, simulation, and validation of high speed designs. Luis holds a BSEE from UC Santa Barbara with an emphasis in Solid State Physics.
Measurement Scientist, Keysight Technologies
Articles

ARTICLES

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Path to 400G May Require Alternative Architectures

DesignCon 2025 Best Paper Award Winner
September 1, 2025
Brandon T. Gore, Richard Mellitz, Andrew Josephson, Francesco de Paulis, Luis Boluña, John Calvin, Rick Rabinovich, and Mike Resso
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Traditional data-center physical layer architectures have undergone a significant transition due to the growth of east-west traffic within the data center for AI/ML cluster applications. This data growth has driven enormous demand for throughput in both chip-to-chip and chip-to-module channels. In this paper, which was awarded Best Paper Award at DesignCon 2025, the authors explore various physical layer design improvements through simulation and modeling tools.



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Are 1.0 mm Precision RF Connectors Required for 224 Gbps PAM4 Verification?

DesignCon 2024 Best Paper Award Winner
October 15, 2024
Brandon T. Gore, Richard Mellitz, Andrew Josephson, Luis Boluña, John Calvin, Rick Rabinovich, and Mike Resso
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This paper, awarded the Best Paper Award at DesignCon 2024, explores what is meant by bandwidth during the standardization process, the implications of test and verification attached to certain bandwidth requirements, as well as differences between acquisition range, band limited filters, and s-parameters for time domain processing. 


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