Signal Integrity

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An Outstanding Paper Award Winner at EDI CON USA 2017, this paper investigates SERDES performance in a multi-board system. The goal is to identify the cause of data transmission errors and variability between different differential pairs on the same board and between several boards.  Numerical and experimental investigations are carried out on a test board supporting several interfaces operating at 16 Gbps and above, with recommendations to improve performance.    

Design of PCB interconnects for data channels running at bitrate 50 Gbps and beyond is a very challenging problem that requires analyses and measurements over extremely broad frequency bandwidth from DC to 50 GHz and above. This paper shares our experience in building a practical methodology to make predictable 50 Gbps interconnects models.

This article discusses some of the common SI and EMI issues that can be found using DRCs.

As Dave Dunham from Molex Corp. likes to say, "When designing high-speed serial links beyond 10 GB/s, everything matters." In order to ensure first time success at these speeds, accurate channel modeling is a prerequisite. This is especially true for long backplane channels.

Each of the five experts presented a different approach to incorporating material properties in simulations to accurately predict a channel’s performance. Read on to see what they had to say.

Wondering what IBIS Open Forum actually does? Mike LaBonte lifts the curtain and invites you to learn more about IBIS models.

JitterLabs announces the immediate availability of an independent test program for evaluating reference clock compliance to PCI Express® (PCIe®) v4.0 BASE specifications, covering all four generations of PCIe technologies (2.5 to 16 GT/s).

If you want help measuring things, there’s no cheaper way to do it than this!