Eric Bogatin, Signal Integrity Journal Technical Editor
Eric Bogatin, Signal Integrity Journal Technical Editor RSS FeedRSS

Eric Bogatin_new headshot_100

Eric Bogatin is Technical Editor at Signal Integrity Journal and the Dean of the Teledyne LeCroy Signal Integrity Academy. Additionally, he is an Adjunct Professor at the University of Colorado - Boulder in the ECEE Dept. Eric improves the signal to noise ratio by sorting through all of the information available and finding the best quality content to publish on

Signal Integrity / Power Integrity

A Design Rule Check List

February 12, 2018

I love lists. Mentor Graphics just released a free version of a design rule checker with a list of the top 22 potential problems to watch out for in your next design. The list is free to view and an automated DRC checker with the first eight in the list is available for free download. An automated tool with all 22 is available for purchase.

It’s both a handy reference guide and an automated checker for any layout format. 

No matter how well you understand the design principles, and no matter how much experience you have in designing boards, it’s easy for some problems to slip through the cracks because you just forgot to check that feature, or your design is just too big to manually check. This is where a design rule checker comes in.

Many EDA layout tools have one built in. They are sometimes called an expert system, in that it’s like having an expert sitting next to you, nudging you in the ribs when it notices a feature in your design on its list for which you might want to give a second look.

In the Mentor Graphics HyperLynx DRC, each rule has a short video with a description of what the rule checks and how to set up the constraints.

Here is their list. Even if you don't use this DRC tool, it’s a handy list to pin to your wall.

  1. Impedance target, based on the cross-section geometry
  2. T-fork, special to DDR routing, looking for equal length branches
  3. Differential impedance target, based on the cross section
  4. Differential pair- coupling and skew
  5. Differential pair phase matching- adequate length matching compensation
  6. Decoupling capacitor placement- keeping them close to the IC pins
  7. Metal islands- floating metal created during a copper fill
  8. Nets crossing gaps- should have been #1 in the list
  9. Edge rate- identify nets with fastest edge rates and most sensitive to SI problems
  10. Guard traces- making sure the guard traces have high enough density of ground vias
  11. Long nets- watch out for the longest traces that may need terminations.
  12. Long stubs- should be #2, if routing stub is too long. Can be a killer problem at higher data rates.
  13. Multiple vias- if there are too many via transitions in a signal path.
  14. Termination check- is the termination scheme adequate, and close to the RX
  15. Cross talk coupling- is the coupled length too long for the coupled spacing
  16. Edge rate to period- is the rise time too long compared to the period?
  17. Topology: star- if you use this topology, make sure legs are equal lengths
  18. Via stub length- especially important in very high-speed serial links > 5 Gbps
  19. Topology: fly-by- typical in DDR3 or DDR4. Checks for the lengths of each segment
  20. Decap order- (ed note: I think this is a misleading rule)
  21. Power/gnd width- makes sure the width of power traces are wide enough for the current
  22. Signal supply- makes sure the correct supply lines go to the correct IC pins