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What is special about a material like PTFE that gives it such a low Dk and Df, while an epoxy has such a high Dk and Df? It is all about the chemical structure of the molecules and how they interact. Understanding the connection between chemistry and electrical properties is the starting place to engineer optimized materials for high-speed interconnects.
Architectural decisions depend on the ability to adequately analyze the link. This paper presents a methodology to model and evaluate the performance of both center and edge sampling schemes.
Interested in performance analysis for 100+ Gb/s per lane PAM4 interfaces? This paper takes a detailed look at high-speed serial link error propagation models and different Ethernet coding schemes as part of FEC performance analysis for 100/200/400 GbE systems with 100+ Gb/s per lane PAM4 interfaces.
Looking into advanced error code correction? Many techniques involve forward error correction. But what exactly is that and how does it relate to your design? Cathy Liu spells it out in this article.
There was a time when the signal integrity of connections between digital ICs could be nearly ensured by following one simple rule: don’t connect more than some maximum number of input pins to any single output pin. Often the fanout limit would be around 7. No models, no simulations. Everything we needed was in the thick books of vendor datasheets that filled our shelves, the tree-killing viral precursor to AOL installation CDs. Ah, those were the days!
While a channel may pass a test, the remaining margin and thus its resilience against geometry or material variation in production may not be observable. However, such variations are critical because they may impede the performance or cause high volume manufacturing (HVM) products to fail. This coalition of authors has developed and demonstrated a polynomial chaos expansion (PCE) flow to analyze a full-featured 100GBASE-KR4 link starting from geometry specification to Channel Operating Margin (COM) margin at the receiver. Read on to see their award winning paper on the subject.
Data converter based SerDes designs are gaining popularity due to their architecture flexibility as well as the capability to implement FFE through powerful DSP. This paper provides a theoretical analysis, realistic simulations and practical comparisons between TX side FFE and RX side FFE.
This paper explains the theory, implementation, constraints, and cost of using CTLE, FFE, DFE, and FEC equalization schemes for serial links at and above 112 Gbps.
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