There was a time when the signal integrity of connections between digital ICs could be nearly ensured by following one simple rule: don’t connect more than some maximum number of input pins to any single output pin. Often the fanout limit would be around 7. No models, no simulations. Everything we needed was in the thick books of vendor datasheets that filled our shelves, the tree-killing viral precursor to AOL installation CDs. Ah, those were the days!
Source: Jason Sachs, EmbeddedRelated.com
Back then, a typical 4.7 MHz signal would have traveled about 32 meters, and reflections had already dissipated before that happened. Rise times were too long to generate much crosstalk between those 100 mil-pitched traces. Life would have been perfect, were it not for that fact that it took so many of those SSI and MSI chips to make any significant product design, that those fan-out limits, while the only signal integrity consideration, could not be forgotten.
But the good old days of designing without electrical simulation didn’t last. And when faster edges, higher clock rates, and closer spacing necessitated simulation, SPICE (Simulation Program With Integrated Circuit Emphasis) was there to help. The big change was suddenly finding ourselves needing to have a lot of time of on our hands. Time to pore over the device model SPICE subcircuits and craft SPICE simulation circuits that would connect to them and make them work as expected. And once that was done, there was the time spent waiting for simulations to finish. SLOOOWWW simulations. Signal integrity became expensive, in terms of time, simulation software and computer resources.
IBIS makes life easier
The first IBIS specification (I/O Buffer Information Specification) appeared in 1993, offering a solution. IBIS behavioral models, like the Quad Design XTK (crosstalk) behavioral models that were gaining popularity at the time, simulated much more quickly than SPICE. And if well-constructed, they gave very reasonable accuracy. Just as important, IBIS models were easy to drop into our designs. Whereas SPICE models came with a variety of calling conventions that required close examination and testing to figure out, EDA tools inherently knew how to plug IBIS models into simulation circuits.
Where IBIS eventually fell behind however was in package models. Starting off with per-pin uncoupled RLC package models, IBIS soon added coupled matrix RLC models in 1994, and then uncoupled series cascaded RLC models in 1996. But you could not combine those – there was no coupled model suitable for longer transmission lines with discontinuities such as the transition from pin to bond wire. It remained that way through the years, while the demand for accurate simulation of ever higher speeds called for something better.
Two steps forward and a step backward
At giga-bit speeds, Touchstone files have emerged as a preferred means for modeling on-die and package interconnects, and even the connections between chips. While Touchstone gives us a leap forward in high-speed interconnect modeling, it also reminds us of the days of trying to figure out how to use SPICE models employing a variety of calling conventions.
Today we find ourselves once again going through a manual process to set up simulations in which the ports of a typical Touchstone s-parameter model, which have no formally identified association with the package, die and I/O (input/output) buffer terminals they represent, are correctly connected into the circuit. After unpacking the zip archives that usually bundle the handful or so of files now required for high-speed-digital signal integrity models, EDA tools still make it easy to use the IBIS files. But using the Touchstone files will involve significantly more reading, clicking and typing.
IBIS 7.0 fills the gap
The IBIS 7.0 specification was passed in March of 2019. It adds a number of new changes, but the feature with possibly the greatest impact is Interconnect Modeling Using IBIS-ISS and Touchstone, known to the dedicated colleagues of the IBIS Open Forum who spent almost 5 years hashing out the details of the feature as BIRD 189.7.
Soon it will be possible to unpack a potentially large set of IBIS, Touchstone, and IBIS-ISS (IBIS Interconnect SPICE Subcircuit, a subset of the HSPICE syntax) files, tell your EDA tool to add the IBIS file to its library, and the setup of all files will be done automatically. Voila, all set to start simulating those super high-speed signals. Not only do we get SPICE and Touchstone modeling of interconnect, IBIS recognizes for the first time the distinction between I/O buffer terminals and die pads. The means are provided to model both on-die and package interconnects separately, for both I/O signals and power supply connections, coupled and uncoupled, through every part of the interconnect path.
Example IBIS [Interconnect Model] for Buffer-to-Die Pad Side (Source: IBIS 7.0)
Another major feature in IBIS 7.0 is Back-channel Support. In SerDes channels and DDR5 memory, finding the optimal equalization settings for the transmitter and receiver SerDes, independently, is no longer adequate. IBIS 7.0 allows IBIS-AMI SerDes models to simulate link training sequences that involve a control communication channel between the transmitter and receiver. This new capability allows simulation tools to co-optimize the Tx and Rx equalization to determine the optimal performance of the channel, and to evaluate alternative training sequence algorithms.
While the IBIS 7.0 specification is available now, the IBISCHK7 parser program (and available source code) to ensure that IBIS files are truly IBIS 7.0 compliant is still in the works. It should be available soon, and we can expect EDA tools to announce IBIS 7.0 support shortly after that. Anyone interested in learning more about IBIS can email email@example.com.