Nitin Bhagwath is a Product Architect at Mentor Graphics. He has designed and architected high-speed systems for Hewlett Packard and Cisco for ten years. He has been with the high-speed simulation group at Mentor Graphics since 2012, where he advises simulation design on multi-gigabit SerDes signals, power integrity and DDR memory. Nitin represents Mentor Graphics at the JEDEC memory groups. Nitin has a bachelors in Electronic Engineering from Bangalore University, an MS in EE from Purdue University and an MBA from the Indian Institute of Management, Bangalore.
While a channel may pass a test, the remaining margin and thus its resilience against geometry or material variation in production may not be observable. However, such variations are critical because they may impede the performance or cause high volume manufacturing (HVM) products to fail. This coalition of authors has developed and demonstrated a polynomial chaos expansion (PCE) flow to analyze a full-featured 100GBASE-KR4 link starting from geometry specification to Channel Operating Margin (COM) margin at the receiver. Read on to see their award winning paper on the subject.