Jayaprakash Balachandran

Jayaprakash Balachandran (JP) is with Unified Compute Server (UCS) Group at Cisco, Inc as a Senior Technical Leader. In this role, he is involved in architecting next generation compute server interconnects and Signal-Power integrity design of advanced ASIC packages and PCBs used in data centers. JP also leads OCP/ODSA Chiplet interoperability work stream. He has over 16 years of experience in high-speed design and has a PhD from KUL/IMEC Belgium.


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Data-Efficient Supervised Machine Learning Technique for Practical PCB Noise Decoupling

DesignCon 2023 Best Paper Award Winner

Design of PCB-based PDNs has become a challenge due to rising power consumption, lowering supply voltages, increasing integration density and design complexity. In this paper, we propose an algorithmic procedure using supervised machine learning techniques to provide expert guidance on the PDN design and optimize power supply decoupling capacitors. The proposed method replaces the computationally expensive numerical simulations with faster ANNs.

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Efficient Sensitivity-Aware Assessment of High-Speed Links Using PCE and the Implications for COM

While a channel may pass a test, the remaining margin and thus its resilience against geometry or material variation in production may not be observable. However, such variations are critical because they may impede the performance or cause high volume manufacturing (HVM) products to fail. This coalition of authors has developed and demonstrated a polynomial chaos expansion (PCE) flow to analyze a full-featured 100GBASE-KR4 link starting from geometry specification to Channel Operating Margin (COM) margin at the receiver. Read on to see their award winning paper on the subject.

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