Jayaprakash Balachandran (JP) is with Unified Compute Server (UCS) Group at Cisco Systems Inc. JP has over 15 years of experience in high-speed design and has a PhD in High-Speed Interconnects from IMEC Belgium. He has many peer-reviewed publications and has been an invited speaker in conferences.
While a channel may pass a test, the remaining margin and thus its resilience against geometry or material variation in production may not be observable. However, such variations are critical because they may impede the performance or cause high volume manufacturing (HVM) products to fail. This coalition of authors has developed and demonstrated a polynomial chaos expansion (PCE) flow to analyze a full-featured 100GBASE-KR4 link starting from geometry specification to Channel Operating Margin (COM) margin at the receiver. Read on to see their award winning paper on the subject.