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What is This Material Called FR-4?

Within the PCB industry, FR-4 materials have long been accepted as “standard” materials. However, their use was not specific to the types of board being designed. For today’s high-speed, high-frequency designs, careful engineering and material selection relative to the resin systems and glass weave styles needed will ensure that a product will work as specified, as designed, and as manufactured. In addition, the finish of the copper used in the signal and power layers also needs to be controlled in order to ensure that loss goals are met.


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An Alternative Approach to Analyzing Far-End Crosstalk

Reducing various types of noise such as reflections, mode-conversion, return-path bounce, and crosstalk becomes a serious challenge in signal integrity designs of high data-rate interfaces. In this article, Dror Haviv focuses on the analysis and properties of the FEXT, presenting an alternative way to analyze the FEXT and its properties using the superposition theory of the differential signal and the common signal.


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How Interconnects Work: Anatomy of Crosstalk

Crosstalk in PCB and packaging interconnects is arguably one of the most complicated phenomena that may cause signal degradation. Crosstalk effects can be treated statistically as a deterministic jitter with a bounded distribution, but the distribution is usually not known. A direct analysis of a worst-case crosstalk scenario may lead to a system overdesign. Neglecting it in design may cause a system failure that is difficult to find and fix later in a design process. Distortions caused by crosstalk cannot be corrected by signal conditioning techniques at a receiver side. It is very important to understand the sources of crosstalk, how to quantify it and how to mitigate it efficiently, as Yuriy Shlepnev demonstrates in this installation of the "How Interconnects Work" series.


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Assessing the Accuracy of EM Simulation Tools

Electromagnetic simulation tools will almost always give a result for any problem after pressing the run button. But is the result accurate? A methodology is introduced to establish the best practices for using the Ansys 2D Extractor and HFSS tools that include recommendations for the setup conditions, balancing accuracy, and computation time. With this methodology, an error in the absolute accuracy when solving for some electrical features can be achieved to better than 0.3%.


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The Road from 1 Gbps-NRZ to 224 Gbps-PAM4

Semiconductor signal conditioning and signal recovery innovations have extended data rates by managing allowable signal-to-noise ratio (SNR) at progressively higher Nyquist frequencies. We have experienced how each successive signaling technology increases the electro-mechanical design resolution needed to address the channel physics while respecting the SNR of the chips. These movements throughout the years have provided a baseline of traditional design goals that lead us to better understand today’s 224 Gbps-PAM4 physical layer requirements.


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IEEE802.3dj Work on 200 Gbps per Lane and How Different FEC Options Affect SI

In this article, Cathy Liu discusses how channel error models and FEC performance analysis have been updated according to industry changes, as well as how different Ethernet coding schemes have been studied and simulated for 800GE and 1.6GE systems with 200 Gbps per lane. Liu investigates concatenated FEC with soft-decision decoding for inner code to protect 200 Gbps optical link and the effect of different FEC options on system SI.



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