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Reducing various types of noise such as reflections, mode-conversion, return-path bounce, and crosstalk becomes a serious challenge in signal integrity designs of high data-rate interfaces. In this article, Dror Haviv focuses on the analysis and properties of the FEXT, presenting an alternative way to analyze the FEXT and its properties using the superposition theory of the differential signal and the common signal.

Crosstalk in PCB and packaging interconnects is arguably one of the most complicated phenomena that may cause signal degradation. Crosstalk effects can be treated statistically as a deterministic jitter with a bounded distribution, but the distribution is usually not known. A direct analysis of a worst-case crosstalk scenario may lead to a system overdesign. Neglecting it in design may cause a system failure that is difficult to find and fix later in a design process. Distortions caused by crosstalk cannot be corrected by signal conditioning techniques at a receiver side. It is very important to understand the sources of crosstalk, how to quantify it and how to mitigate it efficiently, as Yuriy Shlepnev demonstrates in this installation of the "How Interconnects Work" series.

In this article, Yuriy Shlepnev provides an overview of Simbeor electromagnetic signal integrity software and highlights its new features.

Semiconductor signal conditioning and signal recovery innovations have extended data rates by managing allowable signal-to-noise ratio (SNR) at progressively higher Nyquist frequencies. We have experienced how each successive signaling technology increases the electro-mechanical design resolution needed to address the channel physics while respecting the SNR of the chips. These movements throughout the years have provided a baseline of traditional design goals that lead us to better understand today’s 224 Gbps-PAM4 physical layer requirements.

In this article, Cathy Liu discusses how channel error models and FEC performance analysis have been updated according to industry changes, as well as how different Ethernet coding schemes have been studied and simulated for 800GE and 1.6GE systems with 200 Gbps per lane. Liu investigates concatenated FEC with soft-decision decoding for inner code to protect 200 Gbps optical link and the effect of different FEC options on system SI.

In just two generations, six different technological revolutions have transformed our economy, our careers, and our quality of life, for better or for worse. Eric Bogatin reflects upon industry progress and explores the potential impact of the latest development in technological innovation, generative AI.

Having determined the amount of CMRR needed for 2-port measurement in the previous installment of this blog, Steve Sandler and  Benjamin Dannan return with a demonstration of how to create a DUT and make a 40 µΩ impedance measurement with the 2-port probe.

As voltage margins for power rails continue to decrease, end-to-end power integrity modeling is already difficult without having to be concerned if all of your simulation models are correct. System designers typically assume that all of the vendor models are correct. So, what does an engineer do if one of the ASIC die models needed for a power integrity simulation is incorrect? 

DesignCon, the premier high-speed communications and system design conference, returns to its home at the Santa Clara Convention Center in Santa Clara, Calif., with technical paper sessions, tutorials, industry panels, product demos, and exhibits, January 30 to February 1, 2024. Group Event Director Suzanne Deffree reflects on the resources, networking, and innovation that DesignCon 2024 will bring.

In the final installment of his article series "DDR5 Electrical and Timing Measurement Techniques," Randy White explores how following a standard workflow for setting up thresholds and timings to distinguish bursts in DDR5 memory interfaces can make design validation much more efficient, ultimately ensuring compliance with specifications and improving system margin by identifying and resolving any issues, especially those related to either read or write transactions.