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Top 10 Articles for 2017

As rated by reader views, here are the Top 10 Articles on Signal Integrity Journal for 2017. Thank you for your readership in 2017, and we look forward to bringing you many more great technical features in 2018!


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Signal Integrity Methodology for Double-Digit Multi-Gigabit Interfaces

This paper suggests methodologies for creating a “virtual prototype” of a serial link pre-design and how to create the associated interconnect and SerDes models that go with it. Topics include: using IBIS-AMI models & building your own; the latest interconnect extraction techniques; and using standards-based compliance kits to automate post-layout analysis and signoff for advanced interfaces like PCI Express Gen 4.


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Debugging High-Speed SERDES Issues in Multi-board Interconnect Systems

An Outstanding Paper Award Winner at EDI CON USA 2017, this paper investigates SERDES performance in a multi-board system. The goal is to identify the cause of data transmission errors and variability between different differential pairs on the same board and between several boards.  Numerical and experimental investigations are carried out on a test board supporting several interfaces operating at 16 Gbps and above, with recommendations to improve performance.    


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Bode Plots are Overrated

I’m not saying control loop stability isn’t important, of course it is. I am saying that whether your focus is power supply design, power integrity or mixed-signal, the Bode plot probably isn’t going to provide you with a reliable or optimum solution. Here are five major reasons for saying this...
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Lessons learned: How to Make Predictable PCB Interconnects for Data Rates of 50 Gbps and Beyond

Design of PCB interconnects for data channels running at bitrate 50 Gbps and beyond is a very challenging problem that requires analyses and measurements over extremely broad frequency bandwidth from DC to 50 GHz and above. This paper shares our experience in building a practical methodology to make predictable 50 Gbps interconnects models.


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Designing Power for Sensitive Circuits

How do you design power for sensitive circuits including LNAs, clocks, and PLL circuits? Although these circuits consume low power, they are sensitive to even very low levels of power rail noise. This EDI CON USA 2017 Outstanind Paper Award wining paper discusses the various noise paths that contribute to the degradation of the sensitive circuit as well as how to optimize, measure, and troubleshoot power supply related noise for these applications.


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