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Practical DDR Testing: Compliance, Validation and Debug

DDR memory interfaces are becoming increasingly common, and present a unique set of challenges to those designing high-speed embedded systems.  This article will examine what DDR interface testing is all about, concentrating primarily on the physical layer and solutions to common problems.
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High Speed Digital Symposium Launches at EDI CON USA 2017

Day two of the three-day conference includes an afternoon symposium on material characterization challenges in high-speed digital design led by session chair Eric Bogatin.

The Electronic Design Innovation Conference and Exhibition (EDI CON) USA announced the addition of a the High-Speed Digital Symposium to its conference line up during the event at the Hynes Convention Center, September 11-13 in Boston, Mass.

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