Voice of the Experts: Signal Integrity
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The articles and columns contained in this section come from members of the Signal Integrity Journal’s Editorial Advisory Board (EAB) and acknowledged experts in the SI field. These authors are often sought after for their advice. In this column area, the EAB and other SI experts will talk about issues related to signal integrity.

Signal Integrity

The Reality of 56/112 Gbps PAM4 Data Transmission

December 3, 2019

AI. High-frequency trading. Cybersecurity. 5G infrastructure.

These and other in-demand applications require the highest-performance silicon.  Fortunately, 56 Gbps PAM4 Ethernet Switches, FPGAs, SerDes and timing silicon are already commercially available. 112 Gbps PAM4 test silicon is also available under NDA, and production 112 Gbps PAM4 silicon is just around the corner.

System architects, PCB designers, SI specialists and other engineers are quickly discovering something.  It is one thing to demonstrate or prototype 56/112 Gbps PAM4 performance.  It is quite another task to achieve production-level consistency at those data rates.  What are some of the challenges?

Sources of Signal Degradation at 56/112 Gbps PAM4

In short, all design detail matters. Take, for instance, the transmission medium.  Most engineers may assume they are using a PCB, but that may not necessarily be the case.  At 56/112 Gbps PAM4 data rates in long range applications, using low noise, high-performance twinax cable assemblies may be a better choice. Fiber optics may also be an option.  Where a PCB is used, laminate material selection is critical to optimized performance.

What other design details can affect performance across the system?  A major goal of a production process is to eliminate or minimize variability of system level design parameters. For example, manufacturing variation occurs at the PCB and component level.  Skew due to PCB fabric weave can affect signal integrity. Additionally, silicon variation, while small, may occur from batch to batch. Specifications like COM help to eliminate these variables in modeling the system.

For interconnect, performance degradation due to temperature variability is often overlooked. Consider a typical signal trace across several different mediums.  Assuming a constant trace length, insertion loss (IL) increases as frequency increases.  But what effect does temperature variability have on the insertion loss in that same trace?


The illustration above shows the impact of temperature on IL across multiple mediums.  At high frequencies (>20 GHz), IL can vary by more ~10db over a temperature range 25°C - 85°C.  While the effects of temperature on IL lessen with high-performance ultra-low-loss materials like MEGTRON 7 and Tachyon, the variability can still be large enough to affect system performance at high data rates.

What is the solution?

Temperature variability and its effect on insertion loss is just one design detail consider.  How can engineers compensate for this and other design details in 56/112 Gbps PAM4 systems?  Signals and systems need to be modeled, simulated, and tested with proper correlation.

In our lab, interconnect product development and channel performance focuses on multi-physics modeling and simulation. The interconnect and the signal channel are modeled and simulated with respect to electrical, mechanical, thermal, and other criteria to optimize performance. As the solutions are simulated and tested, more accurate models are developed via a highly iterative process.

Prototype components and systems are built and tested until test data correlates with simulated data.  This high-precision correlation of simulated and test data provides more accurate models, higher signal margin across the signal channel, and a higher level of engineering confidence in the final interconnect solution.

For more details on this topic, please register here to the technical session High Speed Interconnect Design and Correlation at 112 Gbps PAM4: How does it impact me? From EDI CON Online on this topic. 



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