Featured Stories

RSS

In this article, Bert Simonovich discusses crosstalk, NEXT vs coupled length in stripline, NEXT vs coupled length in microstrip & FEXT. Read on. 

This paper presents two modeling methodologies for ADC-based SerDes that mitigate IBIS-AMI architectural misalignments, and a corresponding model correlation methodology.

Kenneth Wyatt and Steve Sandler are inclined to recommend a solid return plane be used for all DC-DC power conversion. Read on to find out why. 

In this article, Douglas Brooks and Johannes Adam illustrate how the thermal impacts of heated traces and pads are not limited to the board layer on which they exist; read on to see how they are reflected on every board layer above and below them.

In this paper, the signal integrity design challenges of 224Gbps-PAM4 networking system are analyzed, and the key enablement solutions are proposed to meet the end-to-end (E2E) loss budget of ≤ 40 dB.

In Donald Telian’s book he reveals his steps for successful serial links, called the “7 Steps to Successful Serial Links.” In this article, he discusses his most important steps: (one) minimize discontinuities, and (two) manage loss.  

Modern ASIC-based systems can no longer be designed by rules of thumb when it comes to power integrity. In this DesignCon 2022 paper, Ben Dannan et al explain a workflow using lumped-looped models to improve efficiency, while achieving accuracy, and reducing the overall risk to a given system PDN.  

This article shows the impact of using one of the first DDR4-3200 FPGA memory controllers, the Xilinx Versal, interfaced to a UDIMM to show a method for accurately correlating signal integrity simulations to measurement.

In this article, Eric Bogatin uses the issue of power integrity to illustrate why dialog between experts is crucial.