As data rates in high-speed serial links continue to increase, reaching beyond 100 Gb/s, channel losses necessitate more extensive SerDes equalization techniques to achieve adequate system performance. As a result, ADC-based SerDes architectures are becoming more prevalent, especially in long-reach applications, for communication standards above 100 Gb/s. In an ADC-based SerDes, the equalization is divided between analog and digital domains, thus allowing for extensive equalization in the digital domain, which scales well with process nodes. This equalization division, however, introduces a significant deviation from conventional (non-ADC-based) SerDes architectures. At the same time, IBIS-AMI models, which remain a de-facto industry-wide technical link between SerDes vendors and system integrators, rely on conventional SerDes architectural assumptions. In a conventional SerDes, a fully equalized analog waveform is available, enabling the IBIS-AMI models to convey this waveform to signal integrity (SI) simulators, which, in turn, evaluate the link performance. This link performance, derived from the equalized waveform, frequently drives the model correlation. Because the fully equalized analog waveform is not available in ADC-based SerDes, IBIS-AMI modeling and correlation is challenging for the emerging ADC-based SerDes. 

This paper presents two modeling methodologies for ADC-based SerDes that mitigate IBIS-AMI architectural misalignments, and a corresponding model correlation methodology. Leveraging these methodologies, an IBIS-AMI model for a 1-to-112 Gb/s multi-standard ADC-based SerDes IP is built and correlated. These methodologies are also applied to ADC-based SerDes that use maximum likelihood sequence estimation (MLSE), requiring an even further departure from the IBIS-AMI architectural assumptions. MLSE modeling challenges are presented along with the resulting models and their interaction with SI simulators. 

The first modeling methodology follows a channel operating margin (COM) approach, accurately capturing performance rather than architectural details. A time-agnostic oversampling quantizer is introduced into an analog COM reference architecture, between the continuous-time linear equalizer (CTLE) and feed-forward equalizer (FFE), to model the impact of ADC quantization. This technique allows for the approximation of a fully equalized waveform, which is the required output for SI simulators. The resulting SI eye approximation can be used for qualitative rather than quantitative performance estimation; the quantitative performance is captured by the signal-to-noise ratio (SNR) at the receiver sampling phase. Hence, the proposed correlation methodology uses SNR as the correlation metric. 

The second modeling methodology accurately captures an ADC-based architecture, including the time-interleaved ADCs and the subsequent parallel DSP-based sample processing for clock and data recovery. As a result, only fully equalized parallel discrete-time samples are available: these represent the vertical eye opening at data symbol centers, but convey no information about the horizontal eye opening. This breaks the IBIS-AMI interface compliance, as there is insufficient information to construct an eye diagram. However, an eye diagram is approximated by introducing the IBIS bridge, which serializes and up-samples the equalized samples into an IBIS-compliant waveform that SI simulators can use to evaluate link performance by measuring the vertical eye opening or SNR. Because the SNR is available, the proposed SNR-based model correlation methodology remains applicable. 

MLSE leverages residual inter-symbol interference (ISI) and sequence estimation, rather than symbol detection, to improve bit error rate (BER). However, neither the horizontal nor the vertical eye opening is available. A methodology is proposed to integrate MLSE-based receivers into an IBIS-AMI-compatible framework by shifting the role of SNR evaluation from the SI simulator to the receiver IBIS-AMI model. 

The remainder of this paper is organized into four sections. Section 2 highlights IBIS-AMI modeling challenges stemming from architectural differences between conventional (non-ADC-based) SerDes topologies, which are embedded into fundamental IBIS-AMI modeling principles, and the emerging ADC-based SerDes architectures. Section 3 presents three methodologies to overcome IBIS-AMI modeling challenges for ADC-based SerDes architectures. First, a COM-representative IBIS-AMI modeling technique is introduced, following a COM approach to focus on SerDes performance rather than on implementation details, which allows for a simple ADC-based model integration into the IBIS-AMI environment. Second, an architecturally representative IBIS-AMI modeling technique is described, which captures architectural and implementation details of ADC-based SerDes while maintaining compatibility with the IBIS standard. Third, an IBIS-AMI modeling technique suitable for MLSE algorithms is presented. The paper then shifts focus from modeling to correlation methodologies. Section 4 illustrates our proposed SNR-centric model correlation methodology through a correlation example between an IBIS-AMI model and lab measurements for an ADC-based multi-standard 1-to-112 Gb/s SerDes. Finally, Section 5 concludes this paper.

The paper referenced here received the Best Paper Award at DesignCon 2022. To read the entire DesignCon 2022 paper, download the PDF.