The Joint Electron Device Engineering Council (JEDEC) standard defines the maximum speed for DDR4 as 3200 mega transfers per second (MT/s), although the first DDR4-3200 field-programmable gate array (FPGA) memory controller just became available at those speeds to interface to an unbuffered (or unregistered) dual inline memory module (UDIMM). Effectively modeling a DDR4-3200 channel with simultaneous switching outputs (SSO) in simulation is further challenged to ensure DQ compliance specification for eye-opening at an ultra-low 1E-16 BER.

Since DDR4-3200 edge rates are less than 100 ps, modeling high-speed parallel bus memory interfaces has become challenging for signal integrity engineers and even more challenging across multiple boards when only looking at SI models with injected jitter. More so, to ensure higher fidelity modeling, the PDN and VRM are necessary to see the effects of SSO/SSN contributing noise in a DDR4 system. A power-aware SI simulation is possible by including these other components in the system model.

The question is, how accurate are power-aware SI simulation models to the measurement for DDR4-3200 on one of the first DDR4-3200 FPGA memory controllers? How do we account for the measurement probe loading model in a simulation? How does crosstalk impact DDR4-3200? How do we model this effectively and correlate a power-aware SI model to measurement? The intent of this effort is to use one of the first DDR4-3200 FPGA memory controllers, the Xilinx Versal, interfaced to a UDIMM to show a method to accurately correlate signal integrity simulations to measurement. Using correlated models is critical to ensure voltage and timing specifications are met. In addition to end-to-end system-level analysis, all design parameters will be validated through direct measurements. A model correlation process will be shared to highlight best practices with these measurements.

This research effort combines power-aware SI simulation using Keysight ADS and measurement from Rohde & Schwarz test equipment with DDR4 interposers from EyeKnowHow to show how to improve design margins during DDR4-3200 development cycles—at the same time, investigating the effects of SSN on a DDR4-3200 power-aware SI model.

It also analyzes power-aware simulations and measurements to validate design performance on one of the first DDR4-3200 FPGA memory controllers while verifying this design’s electrical performance meets the JEDEC specifications. These power-aware simulations will look at the effects of SSN/SSO while removing the effects of probe loading and de-embedding the interposer present during the measurement.

This effort additionally looks at vendor models, EM extracted models from 3D field solvers, and IBIS models, and shows considerations to properly simulate these models, concluding with actual measurement correlation on the same simulated DDR4-3200 model.

This paper was presented at DesignCon 2022. Download the full PDF here