Signal Integrity

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Abracon expands its line of high-performance ClearClock™ oscillators with the addition of the brand new AK2A and AK3A-series oscillators.

To provide BEV and HEV designers with a faster, more reliable high-voltage circuit protection solution, Microchip Technology has announced the E-Fuse Demonstrator Board, enabled by SiC technology, available in six variants.

By augmenting its cascode offering with seven new e-mode devices, Nexperia now provides designers with the optimum choice of GaN FETs from a single supplier alongside its substantial portfolio of silicon-based power electronics components.

Reduction of microstrip FEXT plays an important role in microwave engineering, as microstrip coupled line backward couplers suffer from poor directivity when not compensated. In this article, Henning Mextorf presents a general approach to improve directivity which does not require a modification of the dimensions of the coupled line structure and provides closed form solutions for optimum capacitor values.

In this article covering next-generation USB technology, Keysight reviews IP/PHY development kits, simulation solutions, and T&M solutions that serve as the foundation for silicon and system integrators to design compliant USB4 Version 2.0 products that meet strict interoperability requirements in the vast Type-C ecosystem.

PCB connector suppliers are often tasked with providing connectors that meet today’s high-speed and high-density requirements. In many cases, these connectors also need to maintain signal integrity under harsh conditions. Such models make it possible to simulate how the connector will interface and perform in its surrounding environment. IEH has partnered with Modelithics to offer 3D geometry models for various IEH hyperboloid connector products.

Successfully designing a PCB with more than one impedance while maintaining a manufacturable and economical product can be a difficult challenge. By examining the histories and uses of various impedances, Lee Ritchey simplifies the process and discusses the ideal impedance for PCB stackup design.

In a tribute to Bob Pease, David Banas explores the concept of unbounded jitter and how it aligns with the concerns of engineers and link designers. In his discussion of the definition, constituents, and practical limits of jitter, Banas embodies the simplistic approach of his hero. 

High-speed digital links at 224 Gbps per lane, device miniaturization, and ultra-low power budgets result in sophisticated systems that are more complex to optimize signal integrity performance and reliability. Engineers require close collaboration and seamless flows from concept to simulation, emulation, and testing to keep up with technology's pace and meet shrinking time-to-market expectations.

This eBook covers how to connect design workflows to make end-to-end high-speed digital design a reality. It will discuss the challenges and trade-offs associated with optimizing design performance for technologies such as PCIe 6.0, USB4 Version 2.0, and USB-C, DDR5, and LPDDR.