Signal Integrity

Thumbnail F7

Impulse Response from Insertion Loss

This article explains how to convert channel insertion loss data in a standard Touchstone file into the channel impulse response for time domain simulations. It also shows how some pre-processing of the Touchstone data can help improve results by eliminating the ringing that results from the use of frequency-limited measurement data. Read on to see how.


Read More
thumb

Options for Copper Beyond 112 Gbps

Future data center and high-speed computation require faster connectivity to meet the increasing set of applications and bandwidth. IEEE and OIF have developed 106-112 Gbps per lane electrical interface specifications P802.3ck1 and CEI-112 G2 for the 400 GbE system. To meet the next-generation system bandwidth requirement, industry and standard bodies recently kicked off new projects aiming at 800 GbE or even higher speeds beyond 1 TbE. So what comes next beyond 112 Gbps for electrical interfaces over copper (Cu) channels? Will it be 224 Gbps?


Read More
Thumb

A Guide for Single-Ended to Mixed-Mode S-parameter Conversions

Signal integrity engineers almost always have to work with S-parameters. If you have not had to work with them yet, then chances are you will sometime in your career. As speed moves up in the double-digit GB/s regime, many industry standards are moving to serial link-based architectures and are using frequency domain compliance limits based on S-parameter measurements.


Read More
1767 thumb

Design for AMI: A New Integrated Workflow for Modeling 56G PAM4 SerDes Systems

In the future, the complexity of circuit implementation will increase dramatically and modeling of high-speed SerDes systems will continue to be a huge challenge. Modeling equalization circuit characteristics has become extremely important to ensure the success of the final platform implementation and provide a strong signal integrity design guide. This paper reviews the common challenges of converting an existing detailed architectural model to an IBIS-AMI model and some of the ways to address these challenges. It also includes an illustration of the workflow to model Intel’s 56G PAM4 SerDes.


Read More
Thumbnail F1

Seriously Funny Science Worth Watching

The Ig Noble Prizes are awarded every year for an individual or group who “did something that makes people laugh and then think.” In our time of increased stress what a perfect combination of activities for engineers to participate and experience: laughing and thinking.


Read More
thumb rev

Convergence: Key to 224 Gbps PAM4 System Design

Convergence in technology is not a new idea. The concept infers that disparate technologies evolve to a closer association or integration over time. Convergence occurs when any number of technologies, such as micro twinax cables, ASIC design, interconnects, advanced IC packaging, and others combine to offer a unique system-level solution. Many see convergence as required for 224 Gbps PAM4 system performance. 


Read More