Signal Integrity

RSS

PCI-SIG today announced the availability of PCI-SIG ATLs providing PCI Express testing and a process for members to become an official testing lab

In this installation of Engineering Nightmares, Robert Haller explores a keystone rule to keep in mind when troubleshooting signal integrity problems. Learn why signal integrity engineers should never perform a measurement or simulation without first anticipating what they expect to see.

Automotive applications present new challenges to high-speed serial technology. Asymmetric, multi-gigabit signaling between sensors, processors, and displays in the unique noise environments of both electric and internal combustion engine vehicles create new problems for signal and power integrity engineers. This paper introduces the signal impairments required for receiver testing in the emerging automotive standards like ASA, MIPI's A-PHY, Automotive Ethernet, and more. Standards specify different sources of noise in different ways, some in the form of time evolutions, others as spectra. This paper focuses on techniques for generating and calibrating each noise source while describing advanced de-embedding techniques and addressing test equipment limitations.

Where do those strange frequency domain “Kramers-Kronig” equations come from? They don’t seem to have any obvious intuitive basis. Looking at their time domain equivalents, however, resolves the mystery and gives us an intuitive understanding of their origin.

The roughness of copper foils has a detrimental effect on signal loss in PCBs. Therefore, reducing roughness is crucial in minimizing signal loss. Nevertheless, roughness is essential to ensure a good adherence between the prepreg and the copper foil. A compromise must be found between adherence and power integrity. This paper presents a novel approach to evaluate signal loss without assuming any specific roughness shape.    

This paper demonstrates a step-by-step correlation methodology adapted for DSP-based PCIe Gen5 and Gen6 IBIS-AMI models where one can measure and directly correlate raw errors out of the DSP on a test setup that is based on the receiver stress eye methodology of the PCIe standard.

Design of PCB-based PDNs has become a challenge due to rising power consumption, lowering supply voltages, increasing integration density and design complexity. In this paper, we propose an algorithmic procedure using supervised machine learning techniques to provide expert guidance on the PDN design and optimize power supply decoupling capacitors. The proposed method replaces the computationally expensive numerical simulations with faster ANNs.

This paper proposes a model that can serve as a tool for evaluating FEC choices in 200+ Gb/s applications. It allows the comparison of the effect of different inner/outer codes and inner-FEC interleaving schemes on post-FEC BER. It can also be used as a tool for system-level transceiver design, allowing designers to see the impact of design choices on the post-FEC BER efficiently.

The Xpeedic EDA 2023 Suite includes 2.5D and 3D signal integrity and power integrity simulation for advanced packaging, along with three platforms to support 3D EM simulation, multi-domain co-simulation, and high-speed system simulation.