Signal Integrity

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When designing circuit boards, a change made to one aspect of the design intended to resolve an issue can cause problems elsewhere. To reduce the problem of soldering on SMA connectors in an edge launch, a significant signal integrity problem has been introduced. This article explores best practices and provides insight into avoiding an inadvertent mistake.

Donald Telian discusses the nature of collaboration between signal integrity engineers and layout engineers, reflecting on how cooperation can be enhanced to promote teamwork, problem-solving, and productivity. 

Crosstalk problems here to stay as long as interconnects are designed as the open waveguiding systems. Thus, understanding and proper quantification of the crosstalk and mitigation of the consequences are important. This article outlines multiple possible ways to quantify the crosstalk: coupling coefficients, frequency domain metrics, time-domain analysis of crosstalk, and a modern statistical approach. 

Intra-pair skew is a crucial metric when working with multiple lines. Its behavior, measurements, and interpretations are closely linked to other forms of signal degradation, making the definition of a single skew value a nuanced issue that requires careful consideration. In this article, Gustavo Blando and Prashant Pappu introduce three distinct methods for measuring skew, providing options for a wide variety of contexts and skew measurement goals.

GL Communications Inc. addressed the press regarding their latest release of the PacketExpert™ 10GX, used for testing Ethernet and IP networks and individual network infrastructure.

Channel operating margin (COM) is a well-documented IEEE standard that has been used successfully since 2014 in the design of channels and specification of interconnect. In this article, Rich Mellitz reflects on the COM origin story and considers the future of the standard.

Microchip Technology announces its second generation low noise chip-scale atomic clock (LN-CSAC), model SA65-LN, in a lower profile height and designed to operate in a wider temperature range, enabling low phase noise and atomic clock stability in demanding conditions.

DesignCon gears up to celebrate its 30th anniversary this January with special events, an expo full of leading suppliers, and its highly regarded education.

Keysight Technologies, Inc. announced the launch of Chiplet PHY Designer 2025, its latest solution for high-speed digital chiplet design tailored to AI and data centre applications.

SiTime announces the differential-ended SiT5977 Super-TCXO, the only single-chip timing solution that delivers the most resilient performance for AI compute-nodes with high bandwidth and network synchronization.