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Just because someone has a VNA capable of 60 GHz bandwidth doesn’t mean it will always give the same results. It is not the instrument, but the measurement procedure that seems to influence the quality of the measurements the most.  Read on for information on a recent study from Jason Ellison, Heidi Barnes, and Jose Moreira  as well as 7 tips for improving your measurements.

That’s the question that will trigger your amygdala’s fight or flight response as you encounter the many annoyances that PAM4 brings to your world. Since you’re in a lab rather than a jungle, that fight or flight response might translate into sarcastic cracks like: “Right, that higher BER requirement makes it all so much easier—not.” “Good old NRZ, those were some fine bits. Remind me why I asked for this?” And, “dear NRZ, I never knew how much I loved you until I lost you.”

Get six experts in a room together and you are likely to hear seven different opinions. Not so at the Future of Power Integrity Panel Discussion at DesignCon 2019.  The consensus of this panel of experts is that the future of power integrity will include single processor chips drawing as much as 1000 A and more. Read on for the details of this discussion!

While we all love increased network speed, there is an implied assumption that the backbone speeds of the internet will keep up with this rising demand placed upon it by millions of new 5G devices. PCIe 5.0 (or Gen5) represents the technology that is needed by the computer, data center, and ultimately the 5G wireless industry to enable the next generation of mobile and desktop applications. So, what is PCI Express 5.0 and how does it compare to PCI 4.0? Read on to find out.

A particularly challenging configuration is the edge launch, where connectors are used on the edge of the PCB with a transition to a microstrip trace. A poorly optimized connector footprint leads to degradation of the signal integrity performance, especially at high data rates. This paper identifies the root cause of the problem by showing how the electromagnetic fields behave at the transition area. Then it presents a design methodology, using simulated and measured data, that ensures the quality of high-speed data transmission.

DesignCon highlighted the latest in high-speed digital design with keynotes covering the hot topics in the industry such as quantum computing, 5G, and artificial intelligence. Read this review of the event and exhibition.

eSilicon was in the Samtec booth at DesignCon 2019 presenting their collaboration with Wild River Technology to develop an advanced test system that addresses the difficult signal integrity demands of 56/112G PAM4 operation. The test system design utilizes the upcoming IEEE P370 standard in association with compliance metrics 802.3bs, OIF CEI – 56G PAM4, and COBO to validate the required performance.

Now that you have been working in industry for some years, you know what you regret not learning when you had the chance. This book is your second chance.  Read on for a book review of Electric Circuits, a Primer, by JC Oliver, published by Artech House, 2018.

Executive Q&A with Ken Willis, Product Engineering Architect at Cadence discussing product development, business challenges, and the latest developments in SI/PI design. 

In high-speed circuit designs, power integrity (PI) and electromagnetic interference (EMI) are connected together. When the edge of the cavity created by power (PWR) and ground (GND) planes in PCBs radiates, the peak frequencies in the emissions are the same as the peak frequencies in the cavity self-impedance.