Featured Stories

EDI CON

EDI CON USA 2017 Announces Short Courses

Opening day of the conference features in-depth training with three-hour short courses on RF, microwave and high-speed digital design.

The Electronic Design Innovation Conference and Exhibition (EDI CON) USA, the first industry event to bring together RF/microwave and high-speed digital design engineers and system integrators, announced the addition of a full day of training to its conference program at the Hynes Convention Center, September 11-13 in Boston, Mass.


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TE BLS

Reducing EMI with Board-Level Shields

Reducing electromagnetic interference (EMI) is a key challenge when designing electronic devices. In this article, we will take a look into EMI challenges, the role of board-level shields (BLS) in reducing EMI, and the key criteria to keep in mind when selecting BLS.


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EMC Engr Book

Book Review - A Practical Guide to EMC Engineering

Levent Sevgi, who has worked with electromagnetics for almost three decades, wrote this book to address the breadth of EMC engineering topics that are not covered by more specialized texts: market control, accreditation, calibration, EMC testing and measurement and mitigation.


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F 3

How Much Capacitance Do We Really Get?

We have to use enough capacitors so that the PDN functions properly. At the same time, to keep cost and size in check, we want to avoid overdesign and not use capacitors unnecessarily. Read on for advice on how to find the balance.


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Xilinx

Addressing the 5G Challenge with Highly Integrated RFSoC

Radio transceiver, converters and FPGA on chip

The RFSoC concept does just that integrating the multi giga sample ADCs and DACs within the same silicon as the SoC, which contains the processing system and programmable logic. This offers a much tighter integrated solution providing the potential for both reduced footprint and power dissipation, while providing a direct sampling RF solution for 5G applications. Integration of ADC and DAC is not on its own sufficient to address the challenges.


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Fig

S-parameters: Signal Integrity Analysis in the Blink of an Eye

Emerging 100 Gigabit Ethernet and 400 Gigabit Ethernet requirements for communication networks have put increasing demands on Internet infrastructure. New methods of design, validation, and troubleshooting to optimize high speed digital channels are being employed in the R&D laboratory. This article discusses new concepts for serial link design and analysis as applied to physical layer test and measurement techniques. Novel test fixtures and signal integrity software tools will be discussed in real world applications in the form of design case studies.


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NIWeek2017

Engineer What’s Next – NIWeek 2017

This is the first year that NIWeek has taken place in late May instead of its normal early August time slot and switches permanently to this part of the calendar. NIWeek 2017 kicked off with new CEO Alex Davern paying tribute to Dr. T with a standing ovation from the audience. Read this summary of what happened at NIWeek 2017.


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Elephant

What Exactly is Power Integrity?

Larry Smith and I address this question in the preface to our new book. We found this question to be a little like the story of the five blind people and the elephant. They each are asked, what is an elephant? Depending on what part they were facing, imagined the elephant as that feature: a wall, a rope, a tree trunk, etc.
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