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This method enables designers to create 25+ GT/s vias quickly, deliberately, and with much less uncertainty than the traditional technique. Read on to find out more.

Holey Swiss cheese offers a popular metaphor for describing planes with a high density of clearance holes, usually under a BGA escape. The concern of many designers is the impact on the inductance in the power and ground planes due to all those holes. Since the gaps between them is narrow, won’t they constrict the current, dramatically increasing the series resistance and the loop inductance of the planes?

Rogers Corporation has introduced RO1200™ high speed, extremely low loss laminates. As the demand for faster and more data drives channel speeds of core network infrastructure beyond 50 Gbps, one of the limiting factors in increasing performance is the signal attenuation resulting from the circuit materials.

If you want to reduce the near end channel to channel cross talk in a differential pair, is it better to use tightly coupled or loosely coupled differential pairs? Take a moment to write down your answer so you can’t change it as you read this.

Every RF engineer learns about the Smith Chart their first day studying S-parameters. It’s an important tool for RF applications. Not so for SI applications. But there are some valuable insights a Smith Chart can illuminate.  Here’s how to extract those few nuggets.

This design guide focuses on small form factor and low power IoT products. Even though these sorts of products are not in the same performance class as server motherboards, not paying attention to signal and power integrity design principles at the beginning of the design cycle may require multiple board spins to get your IoT product working.