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I have lost count of the number of times I have been asked to fix an EMC problem, only to find that a shielding box has been designed or purchased to provide XdB up to fMAX. Or a filter has been designed or purchased with a similar specification, but to reduce cost the filter has been mounted on a printed circuit board (PCB) inside the box, with a cable from it entering or exiting the box through a plain connector.

SIJ talked with Martin Stumpf about industry trends, how to foster innovation, and what today’s designers need most from their test equipment.

The 2018 IEEE EMC+SIPI event returned to Long Beach, CA after last visiting in 2011. The event continues to include Signal Integrity & Power Integrity (SIPI) as part of the conference, reflecting the EMC Society’s influence and focus on this critical topic of engineering design.

Here’s a look at how phase noise converts to time-interval error jitter, which is particularly important to those working on reference clocks for high-speed SERDES or sampling clocks. Read on to see how this can help debug systems to reduce sources of timing noise.

Tektronix, Inc., introduced the 6 Series MSO mixed signal oscilloscope. The new oscilloscope extends the performance of midrange oscilloscopes to 8 GHz and delivers a 25 GS/s sample rate simultaneously on all 4 channels. A first for this oscilloscope class, while accommodating the needs of designers working on faster, more complex embedded system designs.

This spring, Molex and Samtec announced a collaboration on next-generation data center solutions. SIJ caught up with Brian Vicich of Samtec, Inc and Brent Hatfield of Molex to find out what that means for engineers.

In more than 30 years of teaching signal integrity, I find the most confusing topic for engineers, even those working in the field for years, is the question of what is the impedance of a transmission line?  Read on to learn about the 5 types of impedance.

Nanosecond-level clock synchronization can be an enabler of a new spectrum of timing- and delay-critical applications in data centers. However, the popular clock synchronization algorithm, NTP, can only achieve millisecond-level accuracy. Current solutions for achieving a synchronization accuracy of 10s-100s of nanoseconds require specially designed hardware throughout the network for combatting random network delays and component noise or to exploit clock synchronization inherent in Ethernet standards for the PHY.