Signal Integrity

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A Unique Hands-on Opportunity to Characterize Interconnects to 50 GHz, sponsored by the IEEE P370 Standards group and Samtec.

Researchers at the National Institute of Standards and Technology (NIST) have invented a new approach to testing multilayered, three-dimensional computer chips that are now appearing in some of the latest consumer devices. The new method may be the answer the semiconductor industry needs to quickly assess the reliability of this relatively new chip construction model, which stacks layers of flat circuitry atop one another like floors in a building to help make chips ever-faster and packed with features.

This paper suggests methodologies for creating a “virtual prototype” of a serial link pre-design and how to create the associated interconnect and SerDes models that go with it. Topics include: using IBIS-AMI models & building your own; the latest interconnect extraction techniques; and using standards-based compliance kits to automate post-layout analysis and signoff for advanced interfaces like PCI Express Gen 4.

Keysight Technologies' corporate headquarters in Santa Rosa, California has resumed operations after being temporarily closed due to the wildfires in Northern California. All four main buildings at the site are intact, and the majority of production facilities are back in operation, according to the company. Keysight affirmed the fourth quarter 2017 financial guidance provided in its third quarter earnings release on August 30, 2017.

An Outstanding Paper Award Winner at EDI CON USA 2017, this paper investigates SERDES performance in a multi-board system. The goal is to identify the cause of data transmission errors and variability between different differential pairs on the same board and between several boards.  Numerical and experimental investigations are carried out on a test board supporting several interfaces operating at 16 Gbps and above, with recommendations to improve performance.    

Design of PCB interconnects for data channels running at bitrate 50 Gbps and beyond is a very challenging problem that requires analyses and measurements over extremely broad frequency bandwidth from DC to 50 GHz and above. This paper shares our experience in building a practical methodology to make predictable 50 Gbps interconnects models.

This article discusses some of the common SI and EMI issues that can be found using DRCs.

As Dave Dunham from Molex Corp. likes to say, "When designing high-speed serial links beyond 10 GB/s, everything matters." In order to ensure first time success at these speeds, accurate channel modeling is a prerequisite. This is especially true for long backplane channels.