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This paper reviews four levels of VRM models that VRM designers, board level interconnect designers, semiconductor designers, and product managers often use to explore design tradeoffs throughout the PDN system. The choice of which one to use involves considering engineers’ levels of expertise and what problems they expect to analyze. Some tradeoffs and relative merits of the models are described.
PCIe Gen4 enables new wave of innovation to guide inner-loop SerDes optimization assisted by outer-loop system optimization. This paper introduces an outer-layer equalization scheme for managing SerDes inner-layer equalization to optimize overall system-level aggregate performance.
What does it take to design PCB interconnects with good analysis-to-measurement correlation up to 40 GHz? Is it doable with typical low-cost PCB materials and fabrication process, typical trace width, via back-drilling and the shortage of space to place the stitching vias? This paper reports lessons learned from validation projects with the goal to build a formal procedure for systematic prediction of interconnect behavior up to 40 GHz. Topics include: selection of test structures, connectors and measurement equipment, and analysis uncertainties.
In the GB/s regime, accurate modeling of insertion loss and phase delay is a precursor to successful high-speed serial link designs. We propose a causal (physically meaningful) form of the Hammerstad and Cannonball-Huray metal roughness frequency dependent complex correction factor. Compared to the widely used, non-causal form, it considerably increases the inductive component of internal metal impedance. Transmission lines simulated with a causal version demonstrate increased phase delay and characteristic impedance. By obtaining the dielectric and roughness parameters solely from manufacturers' data sheets, we validate the model through a detailed case study to test its accuracy.
In case you could not make it to EDI CON USA or just want a quick review of the event, here is summary of the keynotes, conference sessions and product review.
The third Electronic Design Innovation Conference (EDICON), was held Oct 17-18, 2018 in Santa Clara. The attendees were treated to two days of technical talks, tutorials and tradeshow with the overlapping topics of RF, SI, PI and EMI. This is a unique combination, allowing cross fertilization between these otherwise separate fields.
We usually associate problems with the power distribution network (PDN) as from excess VRM noise, or from transient current draw from the core or I/O drivers. But that’s not the only source of PDN noise. Some failures can arise from dull, boring, mundane problems at DC.
This paper focuses on the importance of DCD jitter analysis at higher speed and heavier loading NAND systems, and introduces a statistical approach to DCD jitter analysis.
Serial peripheral interface (SPI) is one of the most widely used interfaces between microcontroller and peripheral ICs such as sensors, ADCs, DACs, shift registers, SRAM, and others. This article provides a brief description of the SPI interface followed by an introduction to Analog Devices’ SPI enabled switches and muxes, and how they help reduce the number of digital GPIOs in system board design.
I have lost count of the number of times I have been asked to fix an EMC problem, only to find that a shielding box has been designed or purchased to provide XdB up to fMAX. Or a filter has been designed or purchased with a similar specification, but to reduce cost the filter has been mounted on a printed circuit board (PCB) inside the box, with a cable from it entering or exiting the box through a plain connector.
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