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While a channel may pass a test, the remaining margin and thus its resilience against geometry or material variation in production may not be observable. However, such variations are critical because they may impede the performance or cause high volume manufacturing (HVM) products to fail. This coalition of authors has developed and demonstrated a polynomial chaos expansion (PCE) flow to analyze a full-featured 100GBASE-KR4 link starting from geometry specification to Channel Operating Margin (COM) margin at the receiver. Read on to see their award winning paper on the subject.

This detailed analysis offers a comparison of various calibration methods for pulse generators according to IEC/EN 55016-1-1 (CISPR 16-1-1), where the spectrum amplitude is measured using different methods and then the results are compared and the measurement uncertainty is determined.

Data converter based SerDes designs are gaining popularity due to their architecture flexibility as well as the capability to implement FFE through powerful DSP. This paper provides a theoretical analysis, realistic simulations and practical comparisons between TX side FFE and RX side FFE.

This paper explains the theory, implementation, constraints, and cost of using CTLE, FFE,  DFE, and FEC equalization schemes for serial links at and above 112 Gbps.

This paper is a case study on causality problems in PDNs during power-aware SI simulations. It covers the causality of a PDN, and it reveals the impact on a design if a causality check is not done on the PDN for the package or board.

Since an oscilloscope and phase noise analyzer observe jitter differently, obtaining the same value from both instruments can be challenging. This article presents a phase-noise based methodology that provides similar values as time-interval error jitter derived from an oscilloscope.

It is important in high-speed digital applications to decrease the form factor and increase signal density by reducing isolating metal layers, all while preserving comparable crosstalk, loss and dispersion at the frequency of interest. This paper takes a look at how you can do that by showing how coplanar waveguide with smaller form-factor outperforms stripline in isolation and coupling.

When you make a 2-port shunt through measurement using a commercial vector network analyzer the measurement includes an undesirable ground loop. Left uncorrected, the ground loop introduces significant errors. This paper shows how to solve this problem.

Wondering about the practical uses of the proposed IEEE P370 standard? This  paper shows some applications of the draft IEEE P370 standard in order to demonstrate its effectiveness for interconnect measurement.

The fixtures used to characterize interconnects in complex systems can have a significant effect on the measured data, read on to get the background and perspective on IEEE P370. Check out this Outstanding Paper Award Winner from EDI CON USA 2018.