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Power conversion circuits with control loop(s) are everywhere in electronic systems. We must establish stability and performance metrics for control loops and their circuits. However, generally accepted metrics may not be good enough. Is a crossover frequency with 45 degrees of phase margin and 10 dB of gain margin enough? How can we relate phase margin to peaking in the impedance profile and transient noise requirements? This article aims to answer these and other questions.

VRMs and VRM controllers are often selected based on size, efficiency, price, or a relationship with the manufacturer. This often leads to a poor VRM selection, requiring additional engineering resources, greater time to market, as well as, higher BOM costs to correct the deficiencies. In this article, we evaluate the choices, define some useful figures of merit, and provide specific selection suggestions.

Yuiry Shelpnev argues that simulating a link in isolation from the rest of the board (localization) is probably the most important requirement to simulate interconnects predictably. Read on to understand this important concept.

If we know how to design interconnects that correlate with the measurements for 28 Gbps NRZ, is it going to be a "free lunch" to move to 56 Gbps NRZ? Not so easily, as I learned recently. Read on to see how you can benefit from some analysis and validating your tools.

Power distribution networks (PDNs) delivering power to ICs in a system need to be thoroughly designed and analyzed in order to make sure any voltage fluctuation on the rail is within the tolerance of every IC connected to that rail.  As ICs on the rail draw power, they generate a voltage fluctuation on the rail.  The PDN must have the capacity to supply enough charge such that the resulting voltage drop is less than the maximum voltage drop each IC on the rail can tolerate.  If voltage fluctuations appear outside IC tolerance limits, a slew of problems can surface such as IC damage, failure, or reduced lifespan.

This article presents a method for power integrity analysis in FPGA systems by configuring the FPGA to function as a vector network analyzer (VNA) test instrument for its own power distribution network (PDN).

This article discusses some of the common SI and EMI issues that can be found using DRCs.

The EDI CON USA 2017 keynote speakers addressed the latest engineering trends and challenges in our industry from “in the trenches” stories of design challenges, successes and failures from “Bet Your Job” to “5G in 5 Years” look into the future to a behind the scenes look at T&M. Below are full videos of these featured talks delivered on Sept 12 in Boston.