Get six experts in a room together and you are likely to hear seven different opinions. 

Not so at the Future of Power Integrity Panel Discussion at DesignCon 2019.  The consensus of this panel of experts is that the future of power integrity will include single processor chips drawing as much as 1000 A and more.

Figure 1. Packed room at the Future of Power Integrity panel at DesignCon 2019. Photo courtesy of Mobashar Yazdani, Google.

Mobashar Yazdani, Strategic Semiconductor Commodity Manager at Google moderated the panel and selected the panelists, including:

• Gregory Sizikov Manager, Power Integrity and EMC team in Google’s Hardware Group
• Patrizio Vinciarelli, CEO, Vicor
• Eric Bogatin, Signal Integrity Evangelist, Teledyne LeCroy (full disclosure, that’s me)
• Brian Molloy, Director Strategic Business, Infineon  
• Henry Schrader, Strategic Business mgr for GM Data Center Power, Analog Devices

It used to be, the driving application for server farms was routing traffic on the internet backbone. Now, the driving force at the high end of cloud computing are XPUs, where X is graphics, network or central, Processing Units. It is cloud computing for machine learning, artificial intelligence or neural network processors, each term used interchangeably, that is pushing the limits to power integrity.

Chips are drawing as much as 400 A now, and this will only increase with the next generation of chips already being evaluated.

These high currents offer three huge challenges for the power distribution: getting the DC current to the local VRM, getting the DC current from the local VRM to the die rails, and reducing the voltage noise from transient switching currents.

These driving forces are pushing three important trends.

To reduce the current that is transported on the board, higher voltage rails are being used as power busses in the system. In this environment, the final DC to DC converter has to be very efficient and convert from as much as 12-24 V rails down to 1 V or less rails.

To deliver 1000 A from the local VRM to the die itself, the VRM has to be very close to the die. For 1000 A systems, the requirement is to have the series DC resistance in the 5-10 uOhm range.

Today’s designs are using 6, 2 oz copper layers, just to distribute DC power rail currents. At this thickness, the sheet resistance is 40 uOhms/square. Even with current delivered from all four sides of a square of copper, the series resistance would be 10 uOhms, still too large. And at 10 uOhms, the DC IR power loss for 1000 A would be 10 watts, and this is just in the 6 layers of 2 oz copper.

An alternative is to deliver the 1000 A to the die pads vertically from the VRM into the die bumps through an array of vias.

To reduce the distance from the VRM to the die pads, all potential designs use a VRM built into the package. This includes all switching elements and the LC filters. To reduce size and increase efficiency, much higher switching frequencies in the DC to Dc converters are being considered.

In addition to the DC currents increasing, the core die rail voltages are decreasing. This means that as the transient currents increase, the allowable noise budgets are decreasing, both factors driving the need for higher decoupling capacitance local to the die, integrated with lower loop inductance.

One solution being considered on the die is increased on-die capacitance using deep trenches. Another solution is more and higher value decoupling capacitors in the package. Their rated voltage only needs to be in the 1 V range.

The DC and transient power integrity challenges in the high end XPU class products is as challenging as the signal integrity challenges. While much of DesignCon 2019 focused on getting to the next milestone data rate, it should be noted that there are still plenty of challenges at the lowly DC end of the spectrum, especially in distributing the power to the leading-edge high-performance devices.

“The PDN has reached its limit, if not exceeded,” Henry Schrader said, and it will only get tougher. “If the PDN is not taken into account at the beginning of the design process, the product will not be successful."