Intra-pair skew refers to the time delay between two signals in a differential interface. High-speed interconnects require precise timing synchronization that can be disrupted by even the slightest bit of skew. That is because, as transmission speeds increase, the unit interval (UI) decreases. The result is that digital interfaces supporting current high-speed standards are more susceptible to bit errors. Components such as vias, design decisions like intentionally inserted gaps, and vestigial signals can introduce delays and alter the timing consistency across different signal paths.

The introduction of intra-pair skew in high-speed designs can cause reflections, crosstalk, or bit errors. Overall, signal integrity, and consequently, system reliability, will suffer. Understanding and minimizing interrupted skew helps engineers optimize signal path layouts, improve bandwidth, and ensure robust operation.

Intra-pair skew is especially significant on PAM4 signals. It can reduce the eye size by more than 3X, thereby increasing the signal’s sensitivity to margin. This behavior is even more pronounced when using a differential trace.

PAM4 is the preferred modulation scheme for high-speed interfaces because it significantly improves data speed, yet only requires bandwidth similar to NRZ. Because PAM4 transmits two bits per symbol by using four distinct amplitude levels, it requires precise timing to accurately distinguish between the different levels, especially when signals are close together in time. Therefore, PAM4 signals are highly sensitive to intra-pair skew.

In PAM4, the differential signal when the skew is 0 UI maintains the shape of POS (or the inversion of NEG). When the skew increases, the differential signal is degraded, and it becomes difficult to distinguish 1 or 0 levels as a digital signal. 

 

The Impact of Intra-Pair Skew on BER

The traditional arbitrary intra-pair skew approach uses various coaxial adapters from multiple vendors to introduce an artificial mechanical delay or skew. It has become the conventional method because it allows engineers to step up skew in discrete amounts and allows skew to be introduced anywhere in the channel where there are coaxial connections.

The problem with this method is that it generates skew by creating what is called a trombone trace. In effect, a trombone trace is a routing pattern on a PCB designed to increase the length of one of the traces in a differential pair, thereby compensating for intra-pair skew. It adds a series of bends or loops, which can create significant challenges to accurately characterize designs. The bends and turns often create variations in impedance, leading to signal reflections.

Secondly, a trombone trace on one leg often has a different delay per unit length compared to the straight trace on the other leg. The adverse effect is mode conversion that may negatively impact the signal.

Another major issue with the arbitrary intra-pair skew approach is that the adapters that often introduce the skew can vary in length by as much as ~0.2 in. This makes it difficult to quantify the skew. Further, the method simply cannot truly support higher data rates, in large part because the skew steps are not very granular.

New Test System Configuration
Because the traditional coaxial adapter approach is unsatisfactory for modern high-speed interface designs, an improved test approach is necessary. The new methodology incorporates a high-speed Bit Error Rate Tester (BERT) with integrated PPGs for measuring performance under varying skew conditions.

Enabling this capability requires the use of dual transmitters on the BERT (see Figure 3). Dual transmitters are used for single-ended control of the phase of the signals within the differential pair. The transmitters need to be clock- and jitter-synchronized, yet are independently controlled by phase from the second PPG module. The setup is not currently in the standard CEM Compliance Test configuration, but it is suggested for accurate skew testing. The recommended test setup has a skew on a 64 GT/s differential channel. Differential signals are generated from the outputs of each PPG, allowing for precise control of skew. Both PPGs drive the same pattern, but the second PPG is a logic inversion. Data NEG on both PPGs are terminated at 50 Ω at the source or fed to an oscilloscope. The skewed signal also can be passed through a noise generator, if desired.

The synthesizer serves as the clock source. Optionally, the clock can be fed into a synthesizer from a 100 MHz source. The jitter module is used to produce multiple synchronized clocks to feed each PPG and add jitter. Skew is introduced by a delay block inside each PPG. The delay can be advanced or regressed by dialing skew in POS or NEG direction as needed.

Need for Calibration
Given the precise measurements required to verify today’s high-speed designs, calibration is important for accurate characterization. It ensures the best match between POS and NEG. Parameters that must be matched between the two PPGs during calibration include amplitude, edge rate, duty cycle, jitter, and equalization.

Figure 4 shows results from the test setup. The display reveals the effect of skew on a PAM4 eye at 64 GT/s of a PCIe 6.0 interface with 2 mUI resolution, which is 0.0625 ps for PCIe 6.0. Based on the results, the intra-pair skew can have quantifiable impact to BER margins on PCIe at 64 GT/s, even without any additional impairments.
The increasing speeds of digital interfaces to meet the ever-growing data demands of modern society places stress on design engineers. Conventional test methods cannot support today’s high-speed designs. For this reason, a new test methodology for measuring intra-pair skew is necessary to verify high-speed interfaces such as PCI Express.

The BERT-based setup uses a new method with dual transmitters to control the phase of signals within a differential pair, enabling granular measurement of intra-pair skew. This capability is crucial for understanding and mitigating the impact of skew on BER margins at high data rates such as 64 GT/s.