During DesignCon 2025, I had several side discussions about the findings presented in my DesignCon 2024 paper on dielectric anisotropy.¹ A key concern raised was the discrepancy between measured results and simulations when converting the out-of-plane dielectric constant (Dkz) to in-plane dielectric constant (Dkxy) using my heuristic method. While Isola’s Tachyon 100G showed an average material anisotropy of approximately 4 to 6% across different glass styles, other researchers claimed that an anisotropy of 10 to 12% was necessary for accurate via simulation correlation.⁵

All glass-reinforced laminates are anisotropic, meaning dielectric properties vary depending on the orientation of the electric field within the structure. The Dkxy applies when the electric field is parallel to the fiberglass cloth, whereas the Dkz is when the field is perpendicular to it. Determining material anisotropy is strongly influenced by the specific test method used to extract dielectric properties and knowing the glass to resin volume ratios.

In my DesignCon 2024 paper, I defined percent anisotropy (Λ) as: 

Studies were done in an attempt to determine dielectric anisotropy using a quarter-wave resonant via stub structure.^4,5,6 This approach depends on the time delay (TD), which is influenced by the stub length and is equivalent to one-quarter of the period (T) of the resonant frequency. In theory, this approach seems like a sound method, but in reality, the as-fabricated product can skew the results. 

Any quarter-wave resonant structure generates frequency nulls in the S21 insertion loss (IL), as illustrated in Figure 1. The first resonant null at 13 GHz corresponds to the fundamental frequency (f₀), with additional nulls appearing at each odd-harmonic.

Figure 1. S21 IL plot showing resonant nulls due to quarterwave stub resonances.

Given the speed of light (c), the length of the stub, and the effective dielectric constant (Dkeff) surrounding the via hole structure, the resonant frequency is predicted by:

Adjusting Dk values within a 3D field solver to fit measured results based on as-fabricated PCB cross-section (x-section) dimensions only provides an effective anisotropy (Λeff) specific to a similar via structure utilizing the same dielectric material. It does not represent the true anisotropy of the bulk dielectric. 

While material anisotropy contributes to Dkeff surrounding a via hole structure, several other factors must also be considered. One key factor is resin content of the dielectric. During the lamination process, the prepreg layers are pressed, leading to a decrease in resin volume. Since the glass volume remains unchanged, the overall Dk of the pressed laminate increases. This should be accounted for before applying my heuristic method to calculate Dkxy. 

Another important consideration is drilled hole size. The actual dimensions of the via hole structure often differ from the specifications in the computer aided design (CAD) database, which can impact simulation accuracy.

Lastly, via barrel roughness plays a significant role. Just as foil roughness influences Dkeff and TD in transmission lines, via barrel roughness affects the surrounding dielectric properties as well. Increased via barrel roughness leads to higher TD and lowers the resonant frequency. Since quarter-wave stub resonance is used to determine Λeff, an increase in Dkeff and TD results in higher Λeff values. 

To illustrate the impact of manufacturing tolerances on dielectric anisotropy, an ideal via structure can be compared with an actual fabricated version. An ideal via structure is depicted in Figure 2a. The via barrels are perfectly smooth and antipads align symmetrically across all layers. The dielectric surrounding the via is assumed to be homogeneous. Many signal integrity (SI) engineers rely solely on the bulk Dk values provided in laminate suppliers’ Dk/Df construction tables without accounting for material anisotropy. Additionally, they often assume that the final pressed dielectric thickness matches the stackup design specifications and that the specified drill size aligns with the actual drill bit dimensions.

Figure 2. Cross-section illustration example of an ideal (a) as designed via structure and (b) as-fabricated via structure.

In reality, an as-fabricated x-section reveals deviations from ideal conditions, as illustrated in Figure 2b. Manufacturing tolerances result in misalignment of antipads across layers, and via barrels often exhibit rough surfaces with protruding whiskers which will affect dielectric properties. Moreover, since vias pass through a mixture of resin and fiberglass cloth, using bulk Dk values may not accurately represent material anisotropy. The Dkeff surrounding the via depends on the glass resin volume ratios of the pressed dielectric thickness and actual drill size used.

CAD software defines finished hole size (FHS) in the PCB layout. To add to the confusion, some CAD software also call this drill size. Fabrication notes will specify actual drill diameter tolerances, and the board shop will adjust these to meet plating hole thickness depending on the PCB class the design has to meet. The actual drill diameter is at least 2 mils larger than the FHS, but may be 3 to 4 mils larger depending on the plating requirements specified. When engineering design automation tools import the design database for SI analysis, it is the FHS that gets imported. This is a common trap SI engineers fall into when modeling vias; using the FHS instead of actual drill size will underestimate via capacitance and thus Dkeff.

Via Capacitance
In a coaxial structure, electromagnetic (EM) fields are fully contained within a grounded shield surrounding a central conductor, separated by a dielectric material. The electric field (E-field) dictates capacitance, while the magnetic H-field defines inductance, leading to transverse electromagnetic (TEM) wave propagation.

Although a via structure resembles coaxial design, it lacks a continuous shield. Instead, ground (GND) vias and antipad clearance holes confine EM fields within the dielectric cavity between reference planes, resulting in quasi-TEM propagation. As illustrated in Figure 3, the anatomy of the via structure includes localized EM fields, but does not fully contain them.

Figure 3. Anatomy of a single via structure surrounded by GND reference vias.In Figure 3, Section A-A, via capacitance (Cvia) is influenced by drill diameter (Drillϕ), antipad size (Antipadϕ), and nearby GND vias. Increasing Drillϕ or decreasing Antipadϕ raises via capacitance by reducing the space between the via barrel and antipad. The approximation for via capacitance is given as:

where: ε₀ is the permittivity of free space, Dkxy is the in-plane dielectric constant, and Antipadϕ and Drillϕ represent the antipad and drill diameters, respectively.

Via barrel roughness mainly results from copper plating wicking into voids created by drill bit crazing of the glass reinforcement weave, often due to a dull drill bit. Though typically overlooked in via modeling, it affects SI correlation. Figure 4 illustrates copper plating wicking into glass bundles.

Figure 4. Copper plating wicking into glass crazing caused by drill bit.

Conductor roughness increases via capacitance and Dkeff, similar to how copper surface roughness raises self-capacitance (C₁₁) in transmission lines.² Wicking extends beyond the drill diameter, concentrating electric field strength and further increasing capacitance.

HFSS simulations in Figure 5 validate this effect. Figures 5a and 5b show E-field strength in smooth and rough vias, respectively. The E-field is mostly contained within the antipad opening, like a coaxial geometry. Increased E-field strength along the roughness profile in Figure 5b leads to a 2.6% capacitance rise.

Figure 5. Electric field strength color map and capacitance of (a) smooth vias and (b) rough vias. Source: Juliano Mologni, Ansys.

Achieving model correlation is difficult due to the randomness of wicking and its interaction with glass and resin. A single x-section only captures one slice of the 360° hole, where wicking varies around the circumference. Figure 6 provides a microscopic top-down view of a plated-through hole showing copper wicking into the faintly visible glass weave.

Figure 6. Microscopic top-down view of a slice of an actual plated through hole showing copper wicking into the glass weave, faintly visible running horizontally and vertically.

Dkeff Compensation Due to Conductor Roughness
As shown in Figure 6, the measured inner ring diameter of 14.4 mils represents the FHS. The middle ring drill diameter is 18.43 mils. By inspection, the outer ring diameter of 18.80 mils represents the drill diameter plus the average roughness.

Heuristically, additional capacitance and Dkeff correction due to roughness can be estimated for the via example in Figure 6. If the ratio of Dkeff_rough to Dkeff_smooth is defined as:

If Drillϕsmooth = 18.43 mils; Drillϕrough = 18.80 mils, and assuming a typical Antipadϕ of 40 mils, then by combining Equation 3 with Equation 4, Dkeff_rough can be expressed by Equation 5.


When plugging in the numbers, one sees Dkeff_smooth increases by 2.6% as compared to Dkeff_smooth.

Roughness Effect on TD
Extracting Dkeff from the first quarter-wave resonant null in an S21 IL plot follows Equation 6, which assumes Dkeff is purely capacitance-driven. 

However, for time-variant EM fields, inductance also affects TD. Via barrel roughness impacts self-inductance (L₁₁) similarly to copper surface roughness in transmission lines. In my previous paper,³ Dkeff for time-variant fields is expressed as: 

Since L₁₁ increases Dkeff proportionally, failing to use a causal metal roughness model, such as Bracken’s model,⁷ can lead to misinterpretation of extracted values and anisotropy effects. 

To validate this, I collaborated with Juliano Mologni from Ansys to introduce roughness into a via quarter-wave stub structure and quantify its effect using Equation 6.

A six-layer via stub structure, modeled in HFSS, featured a 10 mil drill, a 50 mil antipad, and six 10 mil stitching vias surrounding main via at 60 mil diameter. Microstrip traces on the top layer extended the stub length to 150 mils. A value of 3.97 was used for Dk.

Applying the Huray roughness model to all vias, parameterized from 0 to 2 μm in 0.1 μm increments (0 to 33 μm Rz equivalent roughness), and an HHSR of 4.9 based on the Simonovich-Cannonball roughness model,⁸ we simulated 20 Huray NR values.

Results
Figure 7 plots S21 IL resonant nulls across all NR values. Each frequency was measured and converted to Dkeff using Equation 6. Dkeff increased from 3.98 for NR = 0 μm to 4.03 for NR = 0.7 μm and did not change for NR increase past that value.
 

Figure 7. S21 IL showing the quarter-wave stub resonant nulls for 0-2 μm Huray nodule radius (NR) roughness parameters. Source: Juliano Mologni, Ansys.

Since Bracken corrects only the imaginary impedance component of rough metal, not capacitance, the observed Dkeff increase is solely attributed to L₁₁ validating the expectation.

Figure 8. Linear fit of Dk vs. prepreg thickness for published values of Tachyon 100G 1078 glass style.

Previous Study 

In a DesignCon 2015 paper,⁴ anisotropic dielectric models were proposed to align via simulations with measurements. Since final results were not available by publication, I reached out to Scott McMorrow, who graciously shared as-fabricated and simulation results.⁵

Two via stub test structures, Stub_1 and Stub_4, were cross-sectioned for analysis. Using measured via lengths and Dk values from the as-designed stackup for the simulation, there was a difference in stub resonance frequency of 1.054% for Stub_1 and 1.057% for Stub_4. These corresponded to as-fabricated effective anisotropy (Λeff) values of 11% and 12%, respectively, based on empirical data.

Figure 9 shows a negative image of the original x-section photo of Stub_1.

Figure 9. Negative image from original cross-section photo of Stub_1 showing pressed dielectric thickness measurements in yellow. Additional measurements for this case study are shown in red. Source: Scott McMorrow.⁵

From the x-section measurements in Figure 9: Drillϕsmooth = 11.80 mils, Drillϕrough = 12.66 mils, and Antipadϕ = 40.04 mils. With Dkeff_smooth = 3.22, Equation 5 yields the effective Dkxy due to roughness (Dkeffxy_rough) as:
 

which increases Dkeffxy by 6.2%.

Excluding Dkeff correction for roughness-induced inductance, the modeled anisotropy of as-fabricated via Stub_1 is:


Taking half the difference between Drillϕrough and Drillϕsmooth, the surface roughness of the via barrel is 0.43 mils or approximately 10.9 μm. Assuming a similar Dkeff contribution as in Reference 5, the polynomial fit shown in Figure 9 suggests this roughness adds 1.36%.

This brings the total effective anisotropy to:
 
Comparison of Simulated vs. Measured Results
Figure 10 shows simulated vs. measured IL.⁵  Using measured stub lengths and Dk values in the HFSS model, the simulated quarter-wave resonant frequency is ~22.1 GHz, while the measured frequency was ~21 GHz. 

Figure 10. Measured vs. simulated IL results.⁵

With a measured stub length of 74.4 mils: 

• Calculated Λeff from Equation 10 = 12.8% 
• Measured Λeff from Equation 14 = 12.5%
• Calculated Dkeff from Equation 11 = 3.61
• Measured Dkeff from Equation 12 = 3.60 

These results confirm excellent correlation and validate the hypothesis. 

The extended case study revealed an effective anisotropy of 12.5%, compared to 4.8% from bulk Dk values. Adjusting Dkeff for pressed thickness and via roughness added ~8%, supporting the need to account for these factors in simulations.

1. B. Simonovich, “A Heuristic Approach to Assess Anisotropic Properties of Glass-reinforced PCB Substrates,” DesignCon 2024 proceedings, Santa Clara, Calif.
2. B. Simonovich, “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness,” DesignCon 2017 proceedings, Santa Clara, Calif.
3. B. Simonovich, “A Tale of Two Data Sheets and How Foil Roughness Affects Dk,” White Paper, Lamsim Enterprises Inc., Issue 03, March 7, 2022.
4. S. McMorrow et al., “Anisotropic Design Considerations for 28 Gbps Via to Stripline Transitions,” DesignCon 2015 proceedings, Santa Clara, Calif.
5. S. McMorrow, “Anisotropy Test Vehicle Tachyon Results,” Samtec presentation, 2022.
6. A. Neves et al., “Free Signal Integrity? How Understanding Anisotropic Materials & Tolerances Could Increase Performance at 112/224Gbps & Beyond,” DesignCon 2025 proceedings, Santa Clara, Calif.
7. J. E. Bracken, “A Causal Huray Model for Surface Roughness.”, DesignCon 2012 proceedings, Santa Clara, CA.
8. B. Simonovich, “Practical Method for Modeling Conductor Surface Roughness Using The Cannonball Stack Principle,” White Paper, Issue 2, April 25, 2015.
9. Isola Tachyon 100G Dk/Df construction table.
10. B. Simonovich, “From Smooth to Imperfect Vias: The Rough Truth Impacting Simulation Model Accuracy,” Signal Integrity Journal, June 3, 2015.

Please note that this is the condensed version of an article that was previously published on the Signal Integrity Journal website in June 2025. The condensed version was published as part of the Signal Integrity Journal October 2025 issue, both online and in print. If you are interested learning more or viewing further data and insights, please click here to redirect to the extended version of the article.