Over the past two decades, the PCI Express (PCIe) standard has successfully doubled its per-lane bandwidth across seven generations while maintaining full backward compatibility. PCIe Gen8 continues this legacy, targeting 256 GT/s per lane using PAM4 signaling, which was first introduced in PCIe Gen6, superseding the NRZ encoding used through Gen5. However, with each new generation, achieving backward compatibility within the same mechanical envelope becomes increasingly complex. The Gen7 transition already pushed the limits of connector and footprint optimization, as detailed in the author’s previous study on Gen6-to-Gen7 signal-integrity transitions.¹

Signal-Integrity Scaling and Frequency Extension

In PCIe Gen7, the specification extended frequency masks to 1.5× Nyquist (48 GHz) to accommodate the 64 GBd Baud rate.² For PCIe Gen8, this boundary rises further, with Nyquist reaching 64 GHz and a validation target extending to 96 GHz. Consequently, the foremost signal-integrity (SI) challenge for Gen8 is to maintain linear insertion-loss (IL) behavior up to these frequencies while sustaining impedance control, minimizing crosstalk, and preserving the same form factor.

Building upon the Gen7¹ research, which demonstrated that shortening the pad length (from 2.5 mm to 1.8 mm) and rounding the pad edges effectively reduced stubs and mitigated cavity resonance, the Gen8 design aims to further extend the IL roll-off frequency through material and geometrical innovations.

Simulation Methodology and Test Cases

Figure 1 illustrates the Add-In Card (AIC) region of the Gen7 connector, showing a section of the spring-contact structure used as the baseline. The baseline configuration uses 2.0 mm signal pads and a dielectric constant (D_k) = 2.9 with loss tangent (Df) = 0.0017, representing a typical Gen7 high-speed laminate.

Figure 1. Add-In Card (AIC) region of the PCIe Gen7 connector used as the baseline model for Gen8 optimization studies. The signal pad length is 2.0 mm with a dielectric material of Dₖ = 2.9 and Df = 0.0017. Three additional test configurations are analyzed: (1) connector spring-contact stub removal, (2) low-loss dielectric substitution with Dₖ = 2.5 and Df = 0.0009, and (3) pad-stub reduction to 1.8 mm length. A fourth case combines all optimizations.

To evaluate Gen8-level enhancements, four distinct test cases were modeled:

1. Spring contact stub removal within the connector to minimize capacitive discontinuities.
2. Dielectric-material optimization by reducing Dₖ from 2.9 to 2.5 and Df from 0.0017 to 0.0009 to simulate the adoption of next-generation low-loss laminates.
3. Pad stub minimization by shortening the signal-pad length from 2.0 mm to 1.8 mm, further reducing parasitic capacitance.
4. Combined optimization, integrating all three modifications above.

These cases aim to extend IL linearity into the 64–96 GHz range, equivalent to 1× to 1.5× Nyquist.

Insertion Loss Comparison

As shown in Figure 2, the IL comparison across all test cases indicates a progressive improvement in high frequency flatness and delay uniformity. If we examine the 3 dB insertion-loss point, the baseline Gen7 configuration exhibits a roll-off near 46 to 48 GHz, whereas the combined optimization case incorporating stub removal, low-D_k/low-Df dielectric, and reduced pad length shifts this point to approximately 56 to 58 GHz. This represents a notable extension of the usable bandwidth, confirming that co-optimization of connector geometry, pad dimensions, and dielectric parameters can extend the effective frequency range by over 20%.

Figure 2. Insertion loss (IL) comparison of five test cases—baseline and four Gen8 optimization scenarios demonstrating improved high-frequency linearity and extended bandwidth up to 96 GHz. The combined optimization case (stub removal + low-Dₖ/low-Df dielectric + pad-stub reduction) exhibits the most significant IL improvement, indicating over 25 % extension of effective frequency range.

Electrical Channel Budget Evolution and Implications at 64 GHz

The total electrical channel budget comprising on-die terminations, die pads, RC/NRC packages, package vias, breakout routing, routing vias, AC-coupling capacitors, motherboard routing, and the mated CEM connector including the AIC gold fingers was set to –36 dB for PCIe Gen5. With the transition from NRZ to PAM4 signaling in PCIe Gen6, this budget was tightened to –32 dB because PAM4 requires additional signal-to-noise margin.³ For PCIe Gen7, the budget was restored to –36 dB despite the Nyquist frequency doubling from 16 GHz to 32 GHz. Achieving this was only possible using significantly lower-loss PCB materials requiring approximately ≤ 1 dB/in loss at 32 GHz such as Megtron-8 or equivalent ultra–low-loss laminates, along with cleaner interconnect structures to maintain traditional motherboard-plus-AIC PCIe reach.⁴

If this trend is extended to a next-generation system operating near a 64 GHz Nyquist frequency, and assuming PCI-SIG retains a similar end-to-end loss budget of –36 dB to –40 dB (still to be defined), material performance would need to improve further. A proportional scaling of frequency-dependent losses indicates that PCB loss targets would need to drop to roughly ≤ 0.75 dB/in at 64 GHz to preserve the same overall channel reach. In practical terms, this means that maintaining conventional PCIe distances at such high frequencies would require a new class of ultra-low-loss laminates and more optimized connector and package launches than what is currently available.

Conclusion

PCIe Gen8’s pursuit of 256 GT/s per lane demands a meticulous balance of mechanical scaling, advanced materials, and electrical tuning. Further gains hinge on adopting low-D_k/low-Df dielectrics, aggressive stub reduction, and connector co-design to realize the 64–96 GHz performance envelope while retaining full backward compatibility within the PCIe CEM ecosystem.

However, achieving this within the existing mechanical envelope will be increasingly challenging. As design margins tighten, PCIe Gen8 could mark the first generation that could necessitate a new form factor, potentially involving a reduced pitch interface on the AIC and motherboard/baseboard side such as 0.6 mm to shorten electrical lengths and mitigate parasitics. Another viable approach could involve reducing connector height, which would further improve insertion loss performance by lowering the total electrical length. These considerations highlight that sustaining bandwidth scalability beyond Gen7 may ultimately require both electrical and mechanical innovation rather than purely material or footprint optimization.

REFERENCES

1. A. Wander, “Navigating Signal Integrity Challenges: Transitioning from PCIe Gen6 to Gen7,” Signal Integrity Journal, April 2024.
2. PCI Express CEM Specification, Revision 7.0, Version 0.5.
3. PCI Express CEM Specification, Revision 6.0, Version 1.0.
4. https://pcisig.com/blog/pcie-70-specification-next-generation-performance-meet-needs-advanced-ai-applications-webinar.