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The development of a low-noise emission PCBs is becoming more difficult because of higher integration densities, faster clock cycles, as well as integrating more radiators like wireless capabilities on to the IC. Based on these design challenges, it is essential to get all of the necessary information for the electric parts before they are placed on a customer’s PCB. Read on for advice on how to detect electromagnetic disturbances above ICs.

In the high-speed connector design arena, there are two opposing ideas. For some people, if you simply put pieces of plastic and metal together, eventually you have a signal transmission. This process is very simple. On the other end of the spectrum, there is the idea that a solid connector design requires a deep understanding of electromagnetic theory, a wisdom only sorcerers and wizards possess.

Read on for a way to combine a BERT and an oscilloscope for actual-time error detection and characterization.

What are the test challenges brought on by PAM4? This article details what a BERT needs to do to meet the necessary signal analysis requirements.

SIJ technical editor, Eric Bogatin, has spent many hours lately watching online training and webinars. He’s launching a regular column to share the ones he thinks are particularly worth watching. Here are his first two picks.

When you need a specialized expert or an assistant for overflow engineering design or analysis work, it’s always a challenge finding a qualified consultant. I get asked for a recommendation for a consultant at least once a week. I tell them to check out the List of SI PI and EMI Consultants on the SI Journal web site, recently updated.

Many claim that for stripline, it is ok to cross a split power plane, so long as the other adjacent reference plane is solid. Some others claim if there is an adjacent solid reference plane, less than 5mils away under the split, crosstalk will be mitigated. Read on to see an investigation into what really happens when stripline signals cross split power planes.

The attenuation in a uniform differential pair has two root causes: conductor loss and dielectric loss. By understanding how design decisions affect these two fundamental root causes, we can develop a few simple guiding principles which point us in the right directions to reduce the attenuation of a channel. These are the directions to follow when loss is important. In some cases, increasing the differential impedance will decrease loss, and in some cases it will increase the loss. Read on to see why.

As DDR data transmission rates continue to increase, the signal integrity of the DDR channel has become one of the most critical concerns. This article takes an extensive look at the impact of via stubs on the impedance of the signal lines on DDR4 memory, including test cases and ways to optimize design.

The first goal in any high-speed board stack up design is to engineer interconnects with a target impedance, and the first step in this process is to use a 2D field solver to explore design space with a virtual prototype. Just how well can a field solver predict the impedance of traces on a real board? This article aims to answer this question.