The first goal in any highspeed board stack up design is to engineer interconnects with a target impedance, and the first step in this process is to use a 2D field solver to explore design space with a virtual prototype. Just how well can a field solver predict the impedance of traces on a real board?
For various projects at the University of Colorado Boulder, we built boards from different vendors and found the measured impedance of traces different from what we expected based on the dimensions and Dk values provided. The difference was more than 15% in a few cases. For some test vehicles that we wanted to use to illustrate signal integrity principles, we needed to engineer specific impedance traces much more accurately. This requirement prompted this study.
Our plan was to use a 2D field solver to accurately predict the impedance of fabricated traces on circuit boards. However, to do this, we needed an accurate value of the dielectric constant, Dk, of the layers. Using an onboard test structure to extract the Dk of the fabricated board, we found that we can routinely achieve trace impedances within less than 3% of our target value. Here is how we did it.
A Test Vehicle
For this experiment, we used the Polar Instruments SI9000 tool as the 2D field solver. The first step was to evaluate the relative accuracy of this tool against other 2D tools. (This was done in [1].) The simulated impedance for the same geometry differential pair transmission lines was found to agree to within 1% for all commercial tools evaluated.
But in practice, how well will the agreement between the prediction of the 2D field solver match the impedance of traces on a fabricated board?
To quickly explore this question, we used an LPKF milling machine to mill out various width uniform transmission lines on a 59 mil thick copper clad circuit board, including the outer copper layers (see Figure 1). Each trace was six inches long. The bottom layer (not visible) was a solid, continuous ground plane.
 Dielectric thickness
 Copper thickness
 Line width
 Dielectric constant
The dielectric thickness was measured as 56.2 mils ±0.5 mils. The copper thickness on both surfaces was 1 oz copper which is assumed to be 1.4 mils thick. The line widths were measured with an optical microscope with an absolute accuracy to within 3%. The last remaining term we needed to input into the 2D field solver was the dielectric constant of the board. When asked, the board vendor said it is 4.2, and all they offered was one value and no idea of the frequency. But is it really Dk = 4.2?
Measuring the Dk
A vendor typically provides a stack up drawing for the dimensions of each layer. Sometimes they do not provide the value of the Dk of each layer, or even worse, sometimes they provide a value, but it turns out to be wrong.
In a previous study, we developed a simple test pattern that is placed on all our boards to measure the Dk of a specific laminate layer. This is a uniform transmission line with two small discontinuities a precision distance apart.
In a TDR measurement of the trace, the roundtrip time delay between the two discontinuities is measured to within 10 psec. From the time delay and length, the signal velocity is calculated, and, from this, the effective Dk. Figure 3 shows a closeup of the small pad that causes the first reflection.
W1 = W2 = 125 mils
T1 = 1.4 mils
Comparing “as Designed” and “as Measured” Impedances
The measured impedance of each line on the board was compared to the calculated value for each line, given the dimensions and the measured bulk Dk of 4.39. This comparison is shown in Figure 6.
Over this range, the worstcase difference was 2.9%. This is the within the absolute accuracy of the line width dimensions.
In this board, the basic uncertainty was in the linewidth, limited by our optical measurement system. Once the Dk was measured, it was possible to predict the characteristic impedance of an as fabricated line to better than 3%.
It is always an important confidence builder when we see a measured value match a simulated value to within the accuracy of the measurement. It doesn’t mean the simulation is correct, it just means that the measurements and the predictions from the 2D field solver are consistent.
This simple experiment demonstrates that with good input information, a 2D field solver can be an accurate predictor of performance.
Designed Target Impedance
Figure 7 is an example of a test line with two small discontinuities spaced exactly 2.0 inches apart and its TDR profile. The measured roundtrip delay between the reflections is 0.635 ±0.01 nsec. The effective Dk is
Using the same process as before, the bulk Dk that we back out for this board is 4.63. This assumes a 1 mil thick soldermask on the top surface. Because of the wide conductor, its impact reduces the impedance by only 0.6% and increases the Dk value by 1%.
The vendor specified Dk of the core was 3.96. This is more than a 17% difference from what we measured. Because we had run previous boards through this vendor’s shop, we knew what the bulk Dk was and designed our test lines using our measured value and not the vendor’s.
Using the bulk Dk of 4.63, the dielectric thickness of the layer and the 2D field solver, we can engineer the line width to achieve a target impedance of 50 Ohms. The measured impedance of this fabricated trace is seen to be 49.5 Ohms, within 1% of the target value. Using this approach, we can engineer any impedance value we need using the 2D field solver.
Conclusion
It is possible to engineer fabricated circuit board traces with target impedances within 1% of the designed impedance using a combination of an accurate 2D field solver, a fab vendor with a stable process, and a special test trace on each board to measure and track the bulk dielectric constant of each layer.
For routine highspeed applications, this level of accuracy is not needed. But, for special test boards that demonstrate specific signal integrity principles, this technique is very important to create predictable interconnect structures.
When the dielectric layers are thinner, and line widths are narrower, the impact of the soldermask plays a slightly larger role. In this case, fabricating a board with test traces having no soldermask will enable better accuracy in the extracted Dk.
While this method was applied to simple 2layer boards in this example, it can be scaled to multilayer boards as well, where the Dk of each layer should be measured to achieve the desired target impedance.
References

Narula, Gaurav, and Eric Bogatin. “Field Solvers for Transmission Line Analysis: How Similar Are They?” Printed Circuit Design & Fab Online Magazine  Field Solvers for Transmission Line Analysis: How Similar Are They?, www.pcdandf.com/pcdesign/index.php/editorial/menufeatures/10472simulation1512.

Bogatin, Eric. “Test Your TDR with a DMM.” Signal Integrity Journal , Signal Integrity Journal, 10 June 2019, www.signalintegrityjournal.com/blogs/8forgoodmeasure/post/1282testyourtdrwithadmm.